From 3a56ed229372fa59e1933ce1291ec0f490dbe623 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 29 Aug 2021 12:10:55 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index f5a2175ce..6e2470a0d 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -119,9 +119,9 @@ in the decoder is greatly increased. # Single Predication -This is a standard mode normally found in Vector ISAs. every element in rvery source Vector and in the destination uses the same bit of one single predicate mask. +This is a standard mode normally found in Vector ISAs. every element in every source Vector and in the destination uses the same bit of one single predicate mask. -Note however that in SVSTATE, implementors MUST increment both srcstep and dststep, and that the two must be equal at all times. +In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times. # Twin Predication -- 2.30.2