From 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b Mon Sep 17 00:00:00 2001 From: Diego H Date: Tue, 26 Nov 2019 17:14:41 -0600 Subject: [PATCH] Adjusting Vivado's BRAM min bits threshold for RAMB18E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..ee961fff8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. + -- 2.30.2