From 3a6c07c1a8159de6b4a20208371de466a0bb1550 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Thu, 7 Jun 2018 03:14:13 +0530 Subject: [PATCH] arch-power: Add fixed-point load and reserve instructions This adds the following load instructions: * Load Byte And Reserve Indexed (lbarx) * Load Halfword And Reserve Indexed (lharx) * Load Doubleword And Reserve Indexed (ldarx) Change-Id: Iac3cf0e16e2b5da8b772be81850419e21f26bdab Signed-off-by: Sandipan Das --- src/arch/power/isa/decoder.isa | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3398e4051..f6cf30b50 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -262,14 +262,17 @@ decode PO default Unknown::unknown() { // Ra and Rb are source registers, Rt is the destintation. format LoadIndexOp { 87: lbzx({{ Rt = Mem_ub; }}); + 52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }}); 279: lhzx({{ Rt = Mem_uh; }}); 343: lhax({{ Rt = Mem_sh; }}); + 116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }}); 790: lhbrx({{ Rt = swap_byte(Mem_uh); }}); 23: lwzx({{ Rt = Mem_uw; }}); 341: lwax({{ Rt = Mem_sw; }}); 20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 534: lwbrx({{ Rt = swap_byte(Mem_uw); }}); 21: ldx({{ Rt = Mem; }}); + 84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }}); 532: ldbrx({{ Rt = swap_byte(Mem); }}); 535: lfsx({{ Ft_sf = Mem_sf; }}); 599: lfdx({{ Ft = Mem_df; }}); -- 2.30.2