From 3a6dd95d6f89c12960a29f58bcfd8e5fbb161275 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 May 2020 16:18:26 +0200 Subject: [PATCH] integration/soc: review/simplify changes for standalone cores. - do the CSR alignment update only if CPU is not CPUNone. - revert PointToPoint interconnect when 1 master and 1 slave since this will break others use cases and will prevent mapping slave to a specific location. It's probably better to let the synthesis tools optimize the 1:1 mapping directly. - add with_soc_interconnect parameter to add_sdram that defaults to True. When set to False, only the LiteDRAMCore will be instantiated and interconnect with the SoC will not be added. --- litex/soc/integration/soc.py | 26 +++++++------------------- litex/soc/integration/soc_core.py | 8 +++----- litex/soc/interconnect/wishbone2csr.py | 10 ++++++---- 3 files changed, 16 insertions(+), 28 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 651f450d..2967daa2 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -781,15 +781,9 @@ class SoC(Module): for n, (origin, size) in enumerate(self.cpu.io_regions.items()): self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False)) self.mem_map.update(self.cpu.mem_map) # FIXME - - # We don't want the CSR alignemnt reduced from 64-bit to 32-bit on - # a standalone system with a 64-bit WB and no CPU. - # Should we instead only update alignment if the CPU is *bigger* - # than the CSR ? - if name != "None": - self.csr.update_alignment(self.cpu.data_width) # Add Bus Masters/CSR/IRQs if not isinstance(self.cpu, cpu.CPUNone): + self.csr.update_alignment(self.cpu.data_width) if reset_address is None: reset_address = self.mem_map["rom"] self.cpu.set_reset_address(reset_address) @@ -830,14 +824,7 @@ class SoC(Module): # SoC Bus Interconnect --------------------------------------------------------------------- bus_masters = self.bus.masters.values() bus_slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()] - # One master and one slave, use a point to point interconnect, this is useful for - # generating standalone components such as LiteDRAM whose external control - # interface is a wishbone. - if len(bus_masters) == 1 and len(bus_slaves) == 1: - self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint( - master = list(bus_masters)[0], - slave = list(self.bus.slaves.values())[0]) - elif len(bus_masters) and len(bus_slaves): + if len(bus_masters) and len(bus_slaves): self.submodules.bus_interconnect = wishbone.InterconnectShared( masters = bus_masters, slaves = bus_slaves, @@ -1010,7 +997,7 @@ class LiteXSoC(SoC): self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) # Add SDRAM ------------------------------------------------------------------------------------ - def add_sdram(self, name, phy, module, origin, size=None, + def add_sdram(self, name, phy, module, origin, size=None, with_soc_interconnect=True, l2_cache_size = 8192, l2_cache_min_data_width = 128, l2_cache_reverse = True, @@ -1032,6 +1019,8 @@ class LiteXSoC(SoC): **kwargs) self.csr.add("sdram") + if not with_soc_interconnect: return + # Compute/Check SDRAM size sdram_size = 2**(module.geom_settings.bankbits + module.geom_settings.rowbits + @@ -1040,8 +1029,7 @@ class LiteXSoC(SoC): sdram_size = min(sdram_size, size) # Add SDRAM region - if self.cpu_type is not None: - self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) + self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) # SoC [<--> L2 Cache] <--> LiteDRAM -------------------------------------------------------- if len(self.cpu.memory_buses): @@ -1092,7 +1080,7 @@ class LiteXSoC(SoC): # Else raise Error. else: raise NotImplementedError - elif self.cpu_type is not None: + else: # When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM. # Request a LiteDRAM native port. diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 6873659c..8a4dd937 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -128,7 +128,7 @@ class SoCCore(LiteXSoC): # Parameters management -------------------------------------------------------------------- cpu_type = None if cpu_type == "None" else cpu_type cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address - cpu_variant = cpu.check_format_cpu_variant(cpu_variant) + cpu_variant = cpu.check_format_cpu_variant(cpu_variant) self.cpu_type = cpu_type self.cpu_variant = cpu_variant @@ -184,10 +184,8 @@ class SoCCore(LiteXSoC): if with_timer: self.add_timer(name="timer0") - # Add CSR bridge. Potentially override CSR base - if csr_base is not None: - self.mem_map["csr"] = csr_base; - self.add_csr_bridge(self.mem_map["csr"]) + # Add CSR bridge + self.add_csr_bridge(self.mem_map["csr"] if csr_base is None else csr_base) # Methods -------------------------------------------------------------------------------------- diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py index c9e30779..14847194 100644 --- a/litex/soc/interconnect/wishbone2csr.py +++ b/litex/soc/interconnect/wishbone2csr.py @@ -10,12 +10,14 @@ from litex.soc.interconnect import csr_bus, wishbone class WB2CSR(Module): def __init__(self, bus_wishbone=None, bus_csr=None): - if bus_csr is None: - bus_csr = csr_bus.Interface() self.csr = bus_csr - if bus_wishbone is None: - bus_wishbone = wishbone.Interface(adr_width=bus_csr.address_width) + if self.csr is None: + # If no CSR bus provided, create it with default parameters. + self.csr = csr_bus.Interface() self.wishbone = bus_wishbone + if self.wishbone is None: + # If no Wishbone bus provided, create it with default parameters. + self.wishbone = wishbone.Interface() # # # -- 2.30.2