From 3ace43b5cdf538cb2ee668eeb27f3b7522c071f3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 22 Dec 2018 07:24:15 +0000 Subject: [PATCH] back.rtlil: remove useless condition. NFC. --- nmigen/back/rtlil.py | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 6fff6d2..e438efb 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -538,16 +538,15 @@ class _StatementCompiler(xfrm.AbstractStatementTransformer): self._case = old_case def on_Assign(self, stmt): - if isinstance(stmt, ast.Assign): - lhs_bits, lhs_sign = stmt.lhs.shape() - rhs_bits, rhs_sign = stmt.rhs.shape() - if lhs_bits == rhs_bits: - rhs_sigspec = self.rhs_compiler(stmt.rhs) - else: - # In RTLIL, LHS and RHS of assignment must have exactly same width. - rhs_sigspec = self.rhs_compiler.match_shape( - stmt.rhs, lhs_bits, rhs_sign) - self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec) + lhs_bits, lhs_sign = stmt.lhs.shape() + rhs_bits, rhs_sign = stmt.rhs.shape() + if lhs_bits == rhs_bits: + rhs_sigspec = self.rhs_compiler(stmt.rhs) + else: + # In RTLIL, LHS and RHS of assignment must have exactly same width. + rhs_sigspec = self.rhs_compiler.match_shape( + stmt.rhs, lhs_bits, rhs_sign) + self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec) def on_Switch(self, stmt): with self._case.switch(self.rhs_compiler(stmt.test)) as switch: -- 2.30.2