From 3ada82639ffd559da8d3f89664ac279ab2280dae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Mar 2020 06:51:03 -0700
Subject: [PATCH] verilog: add test

---
 tests/various/src.ys | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 tests/various/src.ys

diff --git a/tests/various/src.ys b/tests/various/src.ys
new file mode 100644
index 000000000..89d6700ca
--- /dev/null
+++ b/tests/various/src.ys
@@ -0,0 +1,8 @@
+logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
+logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+read_verilog <<EOT
+module top(input i, output o, p);
+always @* o <= i;
+always @* p = i;
+endmodule
+EOT
-- 
2.30.2