From 3add96212bfb23e459a703a54b8e7e0a1551456b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 7 Jul 2012 00:23:56 +0200 Subject: [PATCH] framebuffer: switch to real DMA --- milkymist/framebuffer/__init__.py | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py index 0431d648..0b2faacd 100644 --- a/milkymist/framebuffer/__init__.py +++ b/milkymist/framebuffer/__init__.py @@ -207,25 +207,6 @@ def sim_fifo_gen(): yield t print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])) -class FakeDMA(Actor): - def __init__(self, port): - self.port = port - super().__init__( - ("address", Sink, [("a", BV(self.port.hub.aw))]), - ("data", Source, [("d", BV(self.port.hub.dw))])) - - def get_fragment(self): - pixel = Signal(BV(32)) - comb = [ - self.endpoints["address"].ack.eq(1), - self.endpoints["data"].stb.eq(1), - self.token("data").d.eq(Replicate(pixel, 4)) - ] - sync = [ - If(self.endpoints["data"].ack, pixel.eq(pixel + 1)) - ] - return Fragment(comb, sync) - class Framebuffer: def __init__(self, address, asmiport, simulation=False): asmi_bits = asmiport.hub.aw @@ -237,8 +218,7 @@ class Framebuffer: fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits)) adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits)) adrbuffer = ActorNode(plumbing.Buffer) - #dma = ActorNode(dma_asmi.SequentialReader(asmiport)) - dma = ActorNode(FakeDMA(asmiport)) + dma = ActorNode(dma_asmi.SequentialReader(asmiport)) cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels)) unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout)) vtg = ActorNode(VTG()) -- 2.30.2