From 3afcfe3b53819817057866b528510a9ad12c1854 Mon Sep 17 00:00:00 2001 From: Jordi Vaquero Date: Thu, 9 Apr 2020 11:52:07 +0200 Subject: [PATCH] arch-arm: Fix clasta/b and lasta/b simd&fp instructions The simd&fp version of this instructions required zeroing the result vector except for the first element, that contains the result. Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa/insts/sve.isa | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 06ff728b6..aa4f194ee 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -2432,7 +2432,16 @@ let {{ elif destType == DstRegType.SimdFpScalar: code += ''' else { AA64FpDest_x[0] = AA64FpDestMerge_x[0]; - }''' + } + ''' + if destType == DstRegType.SimdFpScalar: + # This section will extend zeros to the simdFP scalar + # intructions for lasta/b and Clasta/b + code += ''' + for (int i = 1; i < eCount; ++i) { + AA64FpDest_x[i] = (Element)0x0; + } + ''' iop = InstObjParams(name, 'Sve' + Name, 'SveSelectOp', {'code': code, 'op_class': opClass, 'isCond': 'true' if isCond else 'false', -- 2.30.2