From 3afe841d32b7e7dae28b8df006df6f840c396297 Mon Sep 17 00:00:00 2001 From: R Veera Kumar Date: Mon, 22 Nov 2021 10:15:01 +0530 Subject: [PATCH] Add expected state to case_cmpl_microwatt_0_disasm in alu_cases unit test --- src/openpower/test/alu/alu_cases.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py index 33c4e99e..db225674 100644 --- a/src/openpower/test/alu/alu_cases.py +++ b/src/openpower/test/alu/alu_cases.py @@ -333,11 +333,23 @@ class ALUTestCase(TestAccumulatorBase): XER = 0xe00c0000 CR = 0x35055050 + e = ExpectedState(pc=4) + e.intregs[10] = 0xfedf3fff0001c025 + e.intregs[17] = 0x1c026 + e.crregs[0] = 0x3 + e.crregs[1] = 0x5 + e.crregs[3] = 0x5 + e.crregs[4] = 0x5 + e.crregs[6] = 0x5 + e.so = 0x1 + e.ov = 0x3 + e.ca = 0x3 + p = Program(lst, bigendian) p.assembly = '\n'.join(dis)+'\n' self.add_case(p, initial_regs, initial_sprs = {'XER': XER}, - initial_cr = CR) + initial_cr = CR, expected=e) def case_cmplw_microwatt_1(self): """microwatt 1.bin: -- 2.30.2