From 3b074a2e53186b1c18334a7436df419d5a204887 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 5 Dec 2019 11:54:33 -0800 Subject: [PATCH] freedreno/a6xx: disable LRZ when blending Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/a6xx/fd6_blend.c | 4 ++++ src/gallium/drivers/freedreno/a6xx/fd6_blend.h | 1 + src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 5 +++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c index f010b1c507c..6f1ea5e2f79 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c @@ -91,6 +91,8 @@ fd6_blend_state_create(struct pipe_context *pctx, so->base = *cso; + so->lrz_write = true; /* unless blend enabled for any MRT */ + for (i = 0; i < ARRAY_SIZE(so->rb_mrt); i++) { const struct pipe_rt_blend_state *rt; @@ -126,11 +128,13 @@ fd6_blend_state_create(struct pipe_context *pctx, A6XX_RB_MRT_CONTROL_BLEND | A6XX_RB_MRT_CONTROL_BLEND2; mrt_blend |= (1 << i); + so->lrz_write = false; } if (reads_dest) { // so->rb_mrt[i].control |= A6XX_RB_MRT_CONTROL_READ_DEST_ENABLE; mrt_blend |= (1 << i); + so->lrz_write = false; } } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blend.h b/src/gallium/drivers/freedreno/a6xx/fd6_blend.h index d44ed8afb88..e207000bed1 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blend.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blend.h @@ -49,6 +49,7 @@ struct fd6_blend_stateobj { uint32_t rb_blend_cntl; uint32_t rb_dither_cntl; uint32_t sp_blend_cntl; + bool lrz_write; }; static inline struct fd6_blend_stateobj * diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index f5612b6a32d..a44aa3f224c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -696,6 +696,7 @@ build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp) static struct fd_ringbuffer * build_lrz(struct fd6_emit *emit, bool binning_pass) { + struct fd6_blend_stateobj *blend = fd6_blend_stateobj(emit->ctx->blend); struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa); struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer; struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture); @@ -708,7 +709,7 @@ build_lrz(struct fd6_emit *emit, bool binning_pass) if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) { gras_lrz_cntl = 0; rb_lrz_cntl = 0; - } else if (binning_pass && zsa->lrz_write) { + } else if (binning_pass && blend->lrz_write && zsa->lrz_write) { gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE; } @@ -943,7 +944,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit) fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7); } - if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) { + if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) { struct fd_ringbuffer *state; state = build_lrz(emit, false); -- 2.30.2