From 3b24daeeefbcd3f1b42ee825d80c66011cc85d39 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 07:24:15 +0100
Subject: [PATCH] add subvl to headers, comment out state-cfg

---
 riscv/encoding.h   |  6 ++++++
 riscv/processor.cc | 10 +++++-----
 riscv/processor.h  |  7 +++++++
 riscv/sv.h         |  5 +++--
 4 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 77f464e..959bc7f 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -905,13 +905,16 @@
 #define CSR_MSVVL 0x4d0
 #define CSR_MSVMVL 0x4d1
 #define CSR_MSVSTATE 0x4d2
+#define CSR_MSVSUBVL 0x4d4
 #define CSR_SSVVL 0x4e0
 #define CSR_SSVMVL 0x4e1
 #define CSR_SSVSTATE 0x4e2
+#define CSR_SSVSUBVL 0x4e4
 #define CSR_USVVL 0x4f0
 #define CSR_USVMVL 0x4f1
 #define CSR_USVSTATE 0x4f2
 #define CSR_USVCFG 0x4f3
+#define CSR_USVSUBVL 0x4f4
 #define CSR_UREMAP 0x4f7
 #define CSR_USHAPE0 0x4f8
 #define CSR_USHAPE1 0x4f9
@@ -1266,14 +1269,17 @@ DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_R
 #ifdef DECLARE_CSR
 DECLARE_CSR(msvvl, CSR_MSVVL)
 DECLARE_CSR(msvmvl, CSR_MSVMVL)
+DECLARE_CSR(msvsubvl, CSR_MSVSUBVL)
 DECLARE_CSR(msvstate, CSR_MSVSTATE)
 DECLARE_CSR(ssvvl, CSR_SSVVL)
 DECLARE_CSR(ssvmvl, CSR_SSVMVL)
+DECLARE_CSR(ssvsubvl, CSR_SSVSUBVL)
 DECLARE_CSR(ssvstate, CSR_SSVSTATE)
 DECLARE_CSR(usvcfg, CSR_USVCFG)
 DECLARE_CSR(usvstate, CSR_USVSTATE)
 DECLARE_CSR(usvvl, CSR_USVVL)
 DECLARE_CSR(usvmvl, CSR_USVMVL)
+DECLARE_CSR(usvsubvl, CSR_USVSUBVL)
 DECLARE_CSR(svregtop, CSR_SVREGTOP)
 DECLARE_CSR(svregbot, CSR_SVREGBOT)
 DECLARE_CSR(svpredcfg0, CSR_SVPREDCFG0)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index a30c2e3..934a6b0 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -511,17 +511,17 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       reg_t destoffs = get_field(val, SV_STATE_DESTOFFS);
       state.sv().srcoffs  = std::min(srcoffs , state.sv().vl-1);
       state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
-      int state_bank = get_field(val, SV_STATE_BANK);
-      int state_size = get_field(val, SV_STATE_SIZE);
-      set_csr(CSR_USVCFG, state_bank | (state_size << 3));
+      //int state_bank = get_field(val, SV_STATE_BANK);
+      //int state_size = get_field(val, SV_STATE_SIZE);
+      //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
       break;
     }
     case CSR_USVCFG:
     {
       int old_bank = state.sv().state_bank;
       int old_size = state.sv().state_size;
-      state.sv().state_bank = get_field(val, SV_STATE_BANK);
-      state.sv().state_size = get_field(val, SV_STATE_SIZE);
+      state.sv().state_bank = get_field(val, SV_CFG_BANK);
+      state.sv().state_size = get_field(val, SV_CFG_SIZE) >> 3;
       if (old_bank != state.sv().state_bank ||
           old_size != state.sv().state_size)
       {
diff --git a/riscv/processor.h b/riscv/processor.h
index efd8945..8ebade9 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -91,10 +91,17 @@ typedef struct
 #ifdef SPIKE_SIMPLEV
 typedef struct
 {
+  // main vector loop
   uint64_t vl;
   uint64_t mvl;
   int destoffs; // destination loop element offset
   int srcoffs;  // source loop element offset (used in twin-predication)
+
+  // subvector loop
+  uint64_t subvl;
+  int dsvoffs; // destination sub-loop element offset
+  int ssvoffs;  // source sub-loop element offset (used in twin-predication)
+
   int state_size;
   int state_bank;
   sv_reg_csr_entry sv_csrs[SV_UCSR_SZ];
diff --git a/riscv/sv.h b/riscv/sv.h
index 3b6c2e8..fed8b6f 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -112,8 +112,9 @@ typedef struct {
 #define SV_STATE_MVL (0x1f<<6)
 #define SV_STATE_SRCOFFS (0x1f<<12)
 #define SV_STATE_DESTOFFS (0x1f<<18)
-#define SV_STATE_BANK (0x7<<24)
-#define SV_STATE_SIZE (0x3<<27)
+#define SV_STATE_SUBVL (0x3<<24)
+#define SV_STATE_SSVOFFS (0x3<<26)
+#define SV_STATE_DSVOFFS (0x3<<28)
 
 #define SV_CFG_BANK (0x7)
 #define SV_CFG_SIZE (0x3<<3)
-- 
2.30.2