From 3b405d985e789ecf0082f724d2d62d3752e4b60c Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 17 Oct 2019 21:33:54 +0200 Subject: [PATCH] Call memory_dff before DSP mapping to reserve registers (fixes #1447) --- techlibs/ice40/synth_ice40.cc | 1 + techlibs/xilinx/synth_xilinx.cc | 1 + 2 files changed, 2 insertions(+) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b66c6bf57..c942126e1 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { + run("memory_dff"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f13740865..6f8254b59 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -341,6 +341,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { + run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally -- 2.30.2