From 3b49c35c7350b7d149c482f928ddfa4cd7fc64f5 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 10:47:56 +0100
Subject: [PATCH]

---
 openpower/sv/int_fp_mv/appendix.mdwn | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/int_fp_mv/appendix.mdwn b/openpower/sv/int_fp_mv/appendix.mdwn
index 15f6f8c7d..8d091a8ac 100644
--- a/openpower/sv/int_fp_mv/appendix.mdwn
+++ b/openpower/sv/int_fp_mv/appendix.mdwn
@@ -66,7 +66,10 @@ As always with SVP64, some thought and care has to be put into
 how the override behaviour will interact with the base scalar
 operation.
 
-# Equivalent OpenPower ISA v3.0 Assembly Language for FP -> Integer Conversion Modes
+# Power ISA v3.0 Assembly Equivalents<a name="assembler"></a>
+
+Demonstration of how much assembler is needed if these Language-specific
+FP -> Integer Conversion Modes are not available
 
 ## c (IEEE754 standard compliant)
 
@@ -252,7 +255,7 @@ inline Target bitwise_cast(Src v) {
         Target t;
     } u;
     u.s = v;
-…    if (exp < 32) {
+    if (exp < 32) {
         int32_t missingOne = 1 << exp;
         result &= missingOne - 1;
         result += missingOne;
-- 
2.30.2