From 3b6f611b0d3a615f73b97824ff792b712a34177d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 25 Feb 2022 18:48:34 +0000 Subject: [PATCH] get chipselect (cs_n) name right in ECP5DDRPHY has to have a minor workaround to adjust for DFI Interface being named "cs_n" but nmigen-boards convention being "cs" --- gram/phy/ecp5ddrphy.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index f35b760..c644edd 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -140,8 +140,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable): addressbits = len(self.pads.a.o0) bankbits = len(self.pads.ba.o0) nranks = 1 - if hasattr(self.pads, "cs") and hasattr(self.pads.cs, "o0"): - nranks = len(self.pads.cs.o0) + if hasattr(self.pads, "cs_n") and hasattr(self.pads.cs_n, "o0"): + nranks = len(self.pads.cs_n.o0) databits = len(self.pads.dq.io) self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4, name="ecp5phy") @@ -253,6 +253,9 @@ class ECP5DDRPHY(Peripheral, Elaboratable): # dfi.Interface it is "reset" if name == 'rst': name = 'reset_n' + # sigh same for cs + if name == 'cs': + name = 'cs_n' m.d.comb += [ pad.o_clk.eq(ClockSignal("dramsync")), pad.o_fclk.eq(ClockSignal("sync2x")), -- 2.30.2