From 3b74e0fa45a93f23448215ef9148ddc7bcd78cd7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 18 Feb 2020 11:03:38 -0800 Subject: [PATCH] xilinx: add delays to INV --- techlibs/xilinx/cells_sim.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0896f3176..df3b554c1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -160,6 +160,9 @@ module INV( input I ); assign O = !I; + specify + (I => O) = 127; + endspecify endmodule (* abc9_lut=1 *) -- 2.30.2