From 3b9e4c4df69b2178cdb3ce631cef8f990a1818ae Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 25 Nov 2018 12:56:37 -0800 Subject: [PATCH] wishbone.SRAM: Support non-32bit wishbone widths. --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 93a31266..7e8b78d7 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -651,7 +651,7 @@ class SRAM(Module): # generate write enable signal if not read_only: self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i]) - for i in range(4)] + for i in range(bus_data_width//8)] # address and data self.comb += [ port.adr.eq(self.bus.adr[:len(port.adr)]), -- 2.30.2