From 3ba3196f1f680145023b1d37701b659ac9406818 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 01:08:49 +0100
Subject: [PATCH]

---
 openpower/sv/cr_ops.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 375ff81b4..5e59e7bb7 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -176,7 +176,8 @@ Bearing in mind as described in the [[svp64/appendix]] SVP64 Horizontal
 Reduction is a deterministic schedule on top of base Scalar v3.0 operations,
 the same rules apply to CR Operations, i.e. that programmers must
 follow certain conventions in order for an *end result* of a
-reduction to be achieved.  *There are no explicit reduction opcodes*
+reduction to be achieved.  Unlike
+other Vector ISAs *there are no explicit reduction opcodes*
 in SVP64.
 
 Due to these conventions only reduction on operations such as `crand`
-- 
2.30.2