From 3ba62abaf7cdf8aa0d2489414d03baf5a42c0443 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 4 Dec 2023 01:42:31 -0800 Subject: [PATCH] fixedsync/minor_31: add stqcx. because I'm adding the others anyway --- openpower/isa/fixedsync.mdwn | 41 ++++++++++++++++++++++++++++ openpower/isatables/LDSTRM-2P-3S.csv | 1 + openpower/isatables/minor_31.csv | 1 + 3 files changed, 43 insertions(+) diff --git a/openpower/isa/fixedsync.mdwn b/openpower/isa/fixedsync.mdwn index 5a5998f6..13c1f6ef 100644 --- a/openpower/isa/fixedsync.mdwn +++ b/openpower/isa/fixedsync.mdwn @@ -275,3 +275,44 @@ Special Registers Altered: CR0 +# Store Quadword Conditional Indexed + +X-Form + +* stqcx. RSp,RA,RB + +Pseudo-code: + + EA <- (RA|0) + (RB) + undefined_case <- 0 + store_performed <- 0b0 + if RESERVE then + if ((RESERVE_LENGTH = 16) & + (RESERVE_ADDR = real_addr(EA))) then + MEM(EA, 16) <- (RSp) + undefined_case <- 0 + store_performed <- 0b1 + else + # set z to smallest real page size supported by implementation + z <- REAL_PAGE_SIZE + if (RESERVE_ADDR / z) = (real_addr(EA) / z) then + undefined_case <- 1 + else + undefined_case <- 0 + store_performed <- 0b0 + else + undefined_case <- 0 + store_performed <- 0b0 + if undefined_case then + u1 <- undefined(0b1) + if u1 then + MEM(EA, 16) <- (RSp) + u2 <- undefined(0b1) + CR0 <- 0b00 || u2 || XER[SO] + else + CR0 <- 0b00 || store_performed || XER[SO] + RESERVE <- 0 + +Special Registers Altered: + + CR0 diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv index a60fc070..76b2123f 100644 --- a/openpower/isatables/LDSTRM-2P-3S.csv +++ b/openpower/isatables/LDSTRM-2P-3S.csv @@ -14,6 +14,7 @@ stbcix,LDST_IDX,,2P,EXTRA2,EN,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stfiwx,LDST_IDX,,2P,EXTRA2,EN,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0 stdcix,LDST_IDX,,2P,EXTRA2,EN,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0 stwcx,LDST_IDX,,2P,EXTRA2,EN,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 +stqcx,LDST_IDX,,2P,EXTRA2,EN,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 stdcx,LDST_IDX,,2P,EXTRA2,EN,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 stbcx,LDST_IDX,,2P,EXTRA2,EN,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 sthcx,LDST_IDX,,2P,EXTRA2,EN,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0 diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index 07544f21..69a99a77 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -198,6 +198,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b1011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,1,0,0,ONE,0,1,sthcx,X,,, 0b0110110111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthux,X,,, 0b0110010111,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sthx,X,,, +0b0010110110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is8B,0,0,0,1,0,0,ONE,0,1,stqcx,X,,,FIXME: should probably be is16B and RSp 0b1010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,1,0,0,0,0,0,NONE,0,1,stwbrx,X,,, 0b1110010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,cix,0,0,0,NONE,0,1,stwcix,X,,, 0b0010010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is4B,0,0,0,1,0,0,ONE,0,1,stwcx,X,,, -- 2.30.2