From 3bac382f81b4e7a9b7940815821d3cab42ae7700 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Nov 2021 13:41:49 +0000 Subject: [PATCH] make core busy_o part of the CoreOutput data structure the FSM TestIssuer can use this to detect not to send anything to it and the InOrderIssuer can safely ignore it as long as it takes care of RaW hazards --- src/soc/simple/core.py | 8 +++++--- src/soc/simple/issuer.py | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index be4ad559..0602691b 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -126,11 +126,13 @@ class CoreInput: class CoreOutput: def __init__(self): # start/stop and terminated signalling - self.core_terminate_o = Signal(reset=0) # indicates stopped + self.core_terminate_o = Signal() # indicates stopped + self.busy_o = Signal(name="corebusy_o") # at least one ALU busy self.exc_happened = Signal() # exception happened def eq(self, i): self.core_terminate_o.eq(i.core_terminate_o) + self.busy_o.eq(i.busy_o) self.exc_happened.eq(i.exc_happened) @@ -282,7 +284,7 @@ class NonProductionCore(ControlBase): fus = self.fus.fus # indicate if core is busy - busy_o = Signal(name="corebusy_o", reset_less=True) + busy_o = self.o.busy_o # enable/busy-signals for each FU, get one bit for each FU (by name) fu_enable = Signal(len(fus), reset_less=True) @@ -384,7 +386,7 @@ class NonProductionCore(ControlBase): # indicator. BUT, of course, when there is no instruction # we must ignore the fu_found flag, otherwise o_ready will never # be set when everything is idle - comb += self.p.o_ready.eq(~busy_o & (fu_found | ~self.p.i_valid)) + comb += self.p.o_ready.eq(fu_found | ~self.p.i_valid) # return both the function unit "enable" dict as well as the "busy". # the "busy-or-issued" can be passed in to the Read/Write port diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 61e28a74..24830149 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -861,7 +861,7 @@ class TestIssuerInternal(Elaboratable): pdecode2 = self.pdecode2 # temporaries - core_busy_o = ~core.p.o_ready # core is busy + core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy core_ivalid_i = core.p.i_valid # instruction is valid with m.FSM(name="exec_fsm"): @@ -979,7 +979,7 @@ class TestIssuerInternal(Elaboratable): comb += dbg_rst.eq(ResetSignal()) # busy/halted signals from core - core_busy_o = ~core.p.o_ready # core is busy + core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy comb += self.busy_o.eq(core_busy_o) comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i) -- 2.30.2