From 3bada72bb6e3ebb902f9739336c7f8f750727114 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Aug 2020 13:42:04 +0000
Subject: [PATCH] use new "state" regfile

---
 experiments9/cells.lst                    |     1 +
 experiments9/non_generated/test_issuer.il | 40303 +++++++++-----------
 2 files changed, 17091 insertions(+), 23213 deletions(-)

diff --git a/experiments9/cells.lst b/experiments9/cells.lst
index 1e8f149..14c6c78 100644
--- a/experiments9/cells.lst
+++ b/experiments9/cells.lst
@@ -184,6 +184,7 @@ src_l_40
 src_l_56
 src_l_64
 src_l
+state
 st_active
 sto_l
 trap0
diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il
index b03420b..6cbad27 100644
--- a/experiments9/non_generated/test_issuer.il
+++ b/experiments9/non_generated/test_issuer.il
@@ -38868,7 +38868,7 @@ module \dec_a
         switch { $31 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
           case 1'1
-            assign \fast_a 3'010
+            assign \fast_a 3'000
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
@@ -38877,7 +38877,7 @@ module \dec_a
         switch { $35 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
           case 1'1
-            assign \fast_a 3'010
+            assign \fast_a 3'000
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
@@ -38886,19 +38886,19 @@ module \dec_a
         switch \spr
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
-            assign \fast_a 3'010
+            assign \fast_a 3'000
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
-            assign \fast_a 3'011
+            assign \fast_a 3'001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
-            assign \fast_a 3'100
+            assign \fast_a 3'010
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
-            assign \fast_a 3'101
+            assign \fast_a 3'011
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
-            assign \fast_a 3'110
+            assign \fast_a 3'100
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
@@ -39869,10 +39869,10 @@ module \dec_b
         switch { \XL_XO [5] $27 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
           case 2'-1
-            assign \fast_b 3'011
+            assign \fast_b 3'001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
           case 2'1-
-            assign \fast_b 3'100
+            assign \fast_b 3'010
         end
     end
     sync init
@@ -40857,19 +40857,19 @@ module \dec_o
             switch \spr
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
-                assign \fast_o 3'010
+                assign \fast_o 3'000
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
-                assign \fast_o 3'011
+                assign \fast_o 3'001
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
-                assign \fast_o 3'100
+                assign \fast_o 3'010
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
-                assign \fast_o 3'101
+                assign \fast_o 3'011
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
-                assign \fast_o 3'110
+                assign \fast_o 3'100
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
@@ -40886,12 +40886,12 @@ module \dec_o
         switch { $3 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
           case 1'1
-            assign \fast_o 3'010
+            assign \fast_o 3'000
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-        assign \fast_o 3'101
+        assign \fast_o 3'011
     end
     sync init
   end
@@ -41277,12 +41277,12 @@ module \dec_o2
         switch { \lk }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
           case 1'1
-            assign \fast_o 3'011
+            assign \fast_o 3'001
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-        assign \fast_o 3'110
+        assign \fast_o 3'100
     end
     sync init
   end
@@ -41852,10 +41852,10 @@ module \pdecode2
   wire width 1 input 0 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 input 1 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
-  wire width 64 input 2 \dec2_msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
-  wire width 64 input 3 \dec2_pc
+  wire width 64 input 2 \dec2_pc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 input 3 \dec2_msr
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -43353,18 +43353,18 @@ module \pdecode2
     switch { $19 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
       case 1'1
-        assign \fasto1 3'101
+        assign \fasto1 3'011
         assign \fasto1_ok 1'1
-        assign \fasto2 3'110
+        assign \fasto2 3'100
         assign \fasto2_ok 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
     switch { $21 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
       case 1'1
-        assign \fast1 3'101
+        assign \fast1 3'011
         assign \fast1_ok 1'1
-        assign \fast2 3'110
+        assign \fast2 3'100
         assign \fast2_ok 1'1
     end
     sync init
@@ -45720,9 +45720,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe"
 module \pipe
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -47725,7 +47725,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0"
 module \alu_alu0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -47737,7 +47737,7 @@ module \alu_alu0
   wire width 1 output 4 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \xer_so_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 6 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
@@ -48506,9 +48506,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l"
 module \src_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 4 input 2 \s_src
@@ -48651,9 +48651,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l"
 module \opc_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -48796,9 +48796,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l"
 module \req_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 5 output 2 \q_req
@@ -48941,9 +48941,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l"
 module \rst_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -49086,9 +49086,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l"
 module \rok_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -49231,9 +49231,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l"
 module \alui_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -49376,9 +49376,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l"
 module \alu_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -49521,7 +49521,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0"
 module \alu0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -49690,7 +49690,7 @@ module \alu0
   wire width 1 output 38 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 39 \dest5_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 40 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_alu0_n_valid_o
@@ -49923,6 +49923,8 @@ module \alu0
   wire width 5 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 5 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 5 \req_l_r_req$next
   cell \req_l \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -50618,9 +50620,17 @@ module \alu0
     connect \Y $69
   end
   process $group_24
-    assign \req_l_r_req 5'11111
-    assign \req_l_r_req $69
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $69
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 5'11111
+    end
     sync init
+      update \req_l_r_req 5'11111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -52908,9 +52918,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe"
 module \pipe$6
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -53788,7 +53798,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0"
 module \alu_cr0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -53796,7 +53806,7 @@ module \alu_cr0
   wire width 1 output 2 \full_cr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_a_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
@@ -54385,9 +54395,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l"
 module \src_l$10
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 6 input 2 \s_src
@@ -54530,9 +54540,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l"
 module \opc_l$11
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -54675,9 +54685,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l"
 module \req_l$12
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
@@ -54820,9 +54830,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l"
 module \rst_l$13
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -54965,9 +54975,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l"
 module \rok_l$14
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -55110,9 +55120,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l"
 module \alui_l$15
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -55255,9 +55265,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l"
 module \alu_l$16
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -55400,7 +55410,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0"
 module \cr0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -55535,7 +55545,7 @@ module \cr0
   wire width 1 output 23 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 24 \dest3_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 25 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_cr0_n_valid_o
@@ -55723,6 +55733,8 @@ module \cr0
   wire width 3 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \req_l_r_req$next
   cell \req_l$12 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -56418,9 +56430,17 @@ module \cr0
     connect \Y $69
   end
   process $group_24
-    assign \req_l_r_req 3'111
-    assign \req_l_r_req $69
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $69
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 3'111
+    end
     sync init
+      update \req_l_r_req 3'111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -58139,9 +58159,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe"
 module \pipe$19
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -59052,7 +59072,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0"
 module \alu_branch0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \fast1_ok
@@ -59060,7 +59080,7 @@ module \alu_branch0
   wire width 1 output 2 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \nia_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
@@ -59655,9 +59675,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l"
 module \src_l$23
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 input 2 \s_src
@@ -59800,9 +59820,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l"
 module \opc_l$24
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -59945,9 +59965,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l"
 module \req_l$25
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
@@ -60090,9 +60110,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l"
 module \rst_l$26
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -60235,9 +60255,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l"
 module \rok_l$27
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -60380,9 +60400,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l"
 module \alui_l$28
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -60525,9 +60545,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l"
 module \alu_l$29
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -60670,7 +60690,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0"
 module \branch0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 input 1 \oper_i_alu_branch0__cia
@@ -60795,17 +60815,17 @@ module \branch0
   wire width 3 output 18 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 3 input 19 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 20 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 21 \fast2_ok
+  wire width 1 output 20 \fast2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 21 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 22 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 24 \dest3_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 25 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_branch0_n_valid_o
@@ -60993,6 +61013,8 @@ module \branch0
   wire width 3 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \req_l_r_req$next
   cell \req_l$25 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -61688,9 +61710,17 @@ module \branch0
     connect \Y $69
   end
   process $group_24
-    assign \req_l_r_req 3'111
-    assign \req_l_r_req $69
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $69
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 3'111
+    end
     sync init
+      update \req_l_r_req 3'111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__cia
@@ -63849,9 +63879,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe"
 module \pipe$32
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -64862,7 +64892,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0"
 module \alu_trap0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -64874,7 +64904,7 @@ module \alu_trap0
   wire width 1 output 4 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \msr_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 6 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
@@ -65507,9 +65537,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l"
 module \src_l$36
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 4 input 2 \s_src
@@ -65652,9 +65682,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l"
 module \opc_l$37
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -65797,9 +65827,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l"
 module \req_l$38
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 5 output 2 \q_req
@@ -65942,9 +65972,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l"
 module \rst_l$39
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -66087,9 +66117,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l"
 module \rok_l$40
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -66232,9 +66262,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l"
 module \alui_l$41
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -66377,9 +66407,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l"
 module \alu_l$42
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -66522,7 +66552,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0"
 module \trap0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -66653,10 +66683,10 @@ module \trap0
   wire width 64 output 21 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 23 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 24 \fast2_ok
+  wire width 1 output 23 \fast2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 24 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 25 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -66667,7 +66697,7 @@ module \trap0
   wire width 1 output 28 \msr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 29 \dest5_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 30 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_trap0_n_valid_o
@@ -66866,6 +66896,8 @@ module \trap0
   wire width 5 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 5 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 5 \req_l_r_req$next
   cell \req_l$38 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -67561,9 +67593,17 @@ module \trap0
     connect \Y $69
   end
   process $group_24
-    assign \req_l_r_req 5'11111
-    assign \req_l_r_req $69
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $69
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 5'11111
+    end
     sync init
+      update \req_l_r_req 5'11111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -77421,9 +77461,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe"
 module \pipe$45
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -79254,7 +79294,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0"
 module \alu_logical0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -79262,7 +79302,7 @@ module \alu_logical0
   wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \xer_ca_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
@@ -79983,9 +80023,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l"
 module \src_l$51
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 2 input 2 \s_src
@@ -80128,9 +80168,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l"
 module \opc_l$52
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -80273,9 +80313,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l"
 module \req_l$53
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
@@ -80418,9 +80458,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l"
 module \rst_l$54
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -80563,9 +80603,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l"
 module \rok_l$55
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -80708,9 +80748,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l"
 module \alui_l$56
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -80853,9 +80893,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l"
 module \alu_l$57
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -80998,7 +81038,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0"
 module \logical0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -81155,7 +81195,7 @@ module \logical0
   wire width 1 output 32 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 33 \dest3_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 34 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_logical0_n_valid_o
@@ -81374,6 +81414,8 @@ module \logical0
   wire width 3 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \req_l_r_req$next
   cell \req_l$53 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -82069,9 +82111,17 @@ module \logical0
     connect \Y $67
   end
   process $group_24
-    assign \req_l_r_req 3'111
-    assign \req_l_r_req $67
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $67
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 3'111
+    end
     sync init
+      update \req_l_r_req 3'111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -83633,9 +83683,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe"
 module \pipe$60
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -84637,7 +84687,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0"
 module \alu_spr0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -84651,7 +84701,7 @@ module \alu_spr0
   wire width 1 output 5 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \spr1_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 7 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 8 \n_valid_o
@@ -85270,9 +85320,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l"
 module \src_l$63
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 6 input 2 \s_src
@@ -85415,9 +85465,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l"
 module \opc_l$64
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -85560,9 +85610,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l"
 module \req_l$65
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 6 output 2 \q_req
@@ -85705,9 +85755,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l"
 module \rst_l$66
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -85850,9 +85900,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l"
 module \rok_l$67
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -85995,9 +86045,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l"
 module \alui_l$68
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -86140,9 +86190,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l"
 module \alu_l$69
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -86285,7 +86335,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0"
 module \spr0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -86430,7 +86480,7 @@ module \spr0
   wire width 1 output 28 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 29 \dest2_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 30 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_spr0_n_valid_o
@@ -86627,6 +86677,8 @@ module \spr0
   wire width 6 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 6 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 6 \req_l_r_req$next
   cell \req_l$65 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -87322,9 +87374,17 @@ module \spr0
     connect \Y $72
   end
   process $group_24
-    assign \req_l_r_req 6'111111
-    assign \req_l_r_req $72
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $72
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 6'111111
+    end
     sync init
+      update \req_l_r_req 6'111111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -89665,9 +89725,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start"
 module \pipe_start
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 2 \n_valid_o
@@ -91561,9 +91621,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0"
 module \pipe_middle_0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -94050,9 +94110,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end"
 module \pipe_end
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -95683,7 +95743,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0"
 module \alu_div0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -95693,7 +95753,7 @@ module \alu_div0
   wire width 1 output 3 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_so_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 5 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 6 \n_valid_o
@@ -97359,9 +97419,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l"
 module \src_l$80
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 input 2 \s_src
@@ -97504,9 +97564,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l"
 module \opc_l$81
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -97649,9 +97709,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l"
 module \req_l$82
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 4 output 2 \q_req
@@ -97794,9 +97854,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l"
 module \rst_l$83
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -97939,9 +97999,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l"
 module \rok_l$84
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -98084,9 +98144,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l"
 module \alui_l$85
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -98229,9 +98289,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l"
 module \alu_l$86
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -98374,7 +98434,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.div0"
 module \div0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -98537,7 +98597,7 @@ module \div0
   wire width 1 output 35 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 36 \dest4_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 37 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_div0_n_valid_o
@@ -98763,6 +98823,8 @@ module \div0
   wire width 4 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 4 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \req_l_r_req$next
   cell \req_l$82 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -99458,9 +99520,17 @@ module \div0
     connect \Y $68
   end
   process $group_24
-    assign \req_l_r_req 4'1111
-    assign \req_l_r_req $68
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $68
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 4'1111
+    end
     sync init
+      update \req_l_r_req 4'1111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -101587,9 +101657,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1"
 module \mul_pipe1
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 2 \n_valid_o
@@ -103347,9 +103417,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2"
 module \mul_pipe2
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -105563,9 +105633,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3"
 module \mul_pipe3
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -107031,7 +107101,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0"
 module \alu_mul0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -107041,7 +107111,7 @@ module \alu_mul0
   wire width 1 output 3 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_so_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 5 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 6 \n_valid_o
@@ -108465,9 +108535,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l"
 module \src_l$97
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 input 2 \s_src
@@ -108610,9 +108680,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l"
 module \opc_l$98
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -108755,9 +108825,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l"
 module \req_l$99
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 4 output 2 \q_req
@@ -108900,9 +108970,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l"
 module \rst_l$100
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -109045,9 +109115,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l"
 module \rok_l$101
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -109190,9 +109260,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l"
 module \alui_l$102
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -109335,9 +109405,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l"
 module \alu_l$103
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -109480,7 +109550,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0"
 module \mul0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -109633,7 +109703,7 @@ module \mul0
   wire width 1 output 32 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 33 \dest4_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 34 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_mul0_n_valid_o
@@ -109846,6 +109916,8 @@ module \mul0
   wire width 4 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 4 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \req_l_r_req$next
   cell \req_l$99 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -110541,9 +110613,17 @@ module \mul0
     connect \Y $68
   end
   process $group_24
-    assign \req_l_r_req 4'1111
-    assign \req_l_r_req $68
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $68
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 4'1111
+    end
     sync init
+      update \req_l_r_req 4'1111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -113888,9 +113968,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe"
 module \pipe$106
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
@@ -115670,7 +115750,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0"
 module \alu_shift_rot0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \o_ok
@@ -115678,7 +115758,7 @@ module \alu_shift_rot0
   wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \xer_ca_ok
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
@@ -116385,9 +116465,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
 module \src_l$112
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 4 input 2 \s_src
@@ -116530,9 +116610,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
 module \opc_l$113
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -116675,9 +116755,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l"
 module \req_l$114
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
@@ -116820,9 +116900,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l"
 module \rst_l$115
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -116965,9 +117045,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l"
 module \rok_l$116
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
@@ -117110,9 +117190,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l"
 module \alui_l$117
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
@@ -117255,9 +117335,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l"
 module \alu_l$118
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
@@ -117400,7 +117480,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0"
 module \shiftrot0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -117555,7 +117635,7 @@ module \shiftrot0
   wire width 1 output 32 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 33 \dest3_o
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 34 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_shift_rot0_n_valid_o
@@ -117771,6 +117851,8 @@ module \shiftrot0
   wire width 3 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \req_l_r_req$next
   cell \req_l$114 \req_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -118466,9 +118548,17 @@ module \shiftrot0
     connect \Y $68
   end
   process $group_24
-    assign \req_l_r_req 3'111
-    assign \req_l_r_req $68
+    assign \req_l_r_req$next \req_l_r_req
+    assign \req_l_r_req$next $68
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \req_l_r_req$next 3'111
+    end
     sync init
+      update \req_l_r_req 3'111
+    sync posedge \coresync_clk
+      update \req_l_r_req \req_l_r_req$next
   end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -119468,9 +119558,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
 module \opc_l$119
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
@@ -119613,9 +119703,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l"
 module \src_l$120
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 input 2 \s_src
@@ -119758,9 +119848,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l"
 module \alu_l$121
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_alu
@@ -119903,9 +119993,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l"
 module \adr_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_adr
@@ -120048,9 +120138,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l"
 module \lod_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_lod
@@ -120193,9 +120283,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l"
 module \sto_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_sto
@@ -120338,9 +120428,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l"
 module \wri_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_wri
@@ -120483,9 +120573,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l"
 module \upd_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_upd
@@ -120628,9 +120718,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l"
 module \rst_l$122
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
@@ -120773,9 +120863,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l"
 module \lsd_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_lsd
@@ -120918,16 +121008,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
 module \ldst0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 1 \cu_ad__go_i
+  wire width 1 output 1 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 2 \cu_ad__rel_o
+  wire width 1 input 2 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 3 \cu_st__go_i
+  wire width 1 output 3 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 4 \cu_st__rel_o
+  wire width 1 input 4 \cu_st__go_i
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -121058,7 +121148,7 @@ module \ldst0
   wire width 64 output 29 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 30 \ea
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 31 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 32 \ldst_port0_is_ld_i
@@ -121161,6 +121251,8 @@ module \ldst0
   wire width 1 \sto_l_s_sto
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \sto_l_r_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \sto_l_r_sto$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \sto_l_q_sto
   cell \sto_l \sto_l
@@ -121630,9 +121722,17 @@ module \ldst0
     connect \Y $28
   end
   process $group_23
-    assign \sto_l_r_sto 1'1
-    assign \sto_l_r_sto $28
+    assign \sto_l_r_sto$next \sto_l_r_sto
+    assign \sto_l_r_sto$next $28
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \sto_l_r_sto$next 1'1
+    end
     sync init
+      update \sto_l_r_sto 1'1
+    sync posedge \coresync_clk
+      update \sto_l_r_sto \sto_l_r_sto$next
   end
   process $group_24
     assign \lsd_l_s_lsd 1'0
@@ -123144,16 +123244,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus"
 module \fus
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 1 \cu_ad__go_i
+  wire width 1 output 1 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 2 \cu_ad__rel_o
+  wire width 1 input 2 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 3 \cu_st__go_i
+  wire width 1 output 3 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 4 \cu_st__rel_o
+  wire width 1 input 4 \cu_st__go_i
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -124593,16 +124693,16 @@ module \fus
   wire width 1 output 294 \fast1_ok$138
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 295 \fast1_ok$139
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 296 \fast2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 297 \fast2_ok$140
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 296 \dest1_o$140
+  wire width 64 output 298 \dest1_o$141
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 297 \dest2_o$141
+  wire width 64 output 299 \dest2_o$142
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 298 \dest3_o$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 299 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 300 \fast2_ok$143
+  wire width 64 output 300 \dest3_o$143
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 301 \dest2_o$144
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
@@ -124623,7 +124723,7 @@ module \fus
   wire width 1 output 309 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 310 \dest2_o$150
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 311 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 312 \ldst_port0_is_ld_i
@@ -124739,8 +124839,8 @@ module \fus
     connect \fast1_ok \fast1_ok
     connect \cu_wr__rel_o \cu_wr__rel_o$136
     connect \cu_wr__go_i \cu_wr__go_i$137
-    connect \dest1_o \dest1_o$140
     connect \fast2_ok \fast2_ok
+    connect \dest1_o \dest1_o$141
     connect \dest2_o \dest2_o$144
     connect \nia_ok \nia_ok
     connect \dest3_o \dest3_o$147
@@ -124770,8 +124870,8 @@ module \fus
     connect \cu_wr__go_i \cu_wr__go_i$83
     connect \dest1_o \dest1_o$102
     connect \fast1_ok \fast1_ok$138
-    connect \dest2_o \dest2_o$141
-    connect \fast2_ok \fast2_ok$143
+    connect \fast2_ok \fast2_ok$140
+    connect \dest2_o \dest2_o$142
     connect \dest3_o \dest3_o$145
     connect \nia_ok \nia_ok$146
     connect \dest4_o \dest4_o$148
@@ -124844,7 +124944,7 @@ module \fus
     connect \xer_so_ok \xer_so_ok$129
     connect \dest4_o \dest4_o$133
     connect \fast1_ok \fast1_ok$139
-    connect \dest3_o \dest3_o$142
+    connect \dest3_o \dest3_o$143
     connect \spr1_ok \spr1_ok
     connect \dest2_o \dest2_o$150
     connect \coresync_rst \coresync_rst
@@ -124964,10 +125064,10 @@ module \fus
   end
   cell \ldst0 \ldst0
     connect \coresync_clk \coresync_clk
+    connect \cu_st__rel_o \cu_st__rel_o
     connect \cu_ad__go_i \cu_ad__go_i
     connect \cu_ad__rel_o \cu_ad__rel_o
     connect \cu_st__go_i \cu_st__go_i
-    connect \cu_st__rel_o \cu_st__rel_o
     connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
     connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm
     connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok
@@ -125011,16 +125111,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active"
 module \st_active
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 2 \r_st_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_st_active
+  wire width 1 input 3 \s_st_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 3 \q_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_st_active
+  wire width 1 output 4 \q_st_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -125154,18 +125254,18 @@ module \st_active
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active"
-module \ld_active
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done"
+module \st_done
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 3 \q_ld_active
+  wire width 1 input 2 \s_st_done
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_ld_active
+  wire width 1 input 3 \r_st_done
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_st_done
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -125177,7 +125277,7 @@ module \ld_active
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_ld_active
+    connect \A \r_st_done
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -125203,7 +125303,7 @@ module \ld_active
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_ld_active
+    connect \B \s_st_done
     connect \Y $5
   end
   process $group_0
@@ -125226,7 +125326,7 @@ module \ld_active
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_ld_active
+    connect \A \r_st_done
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -125252,16 +125352,16 @@ module \ld_active
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_ld_active
+    connect \B \s_st_done
     connect \Y $11
   end
   process $group_1
-    assign \q_ld_active 1'0
-    assign \q_ld_active $11
+    assign \q_st_done 1'0
+    assign \q_st_done $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_ld_active
+  wire width 1 \qn_st_done
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
@@ -125269,16 +125369,16 @@ module \ld_active
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_ld_active
+    connect \A \q_st_done
     connect \Y $13
   end
   process $group_2
-    assign \qn_ld_active 1'0
-    assign \qn_ld_active $13
+    assign \qn_st_done 1'0
+    assign \qn_st_done $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_ld_active
+  wire width 1 \qlq_st_done
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
@@ -125288,29 +125388,29 @@ module \ld_active
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_ld_active
+    connect \A \q_st_done
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_ld_active 1'0
-    assign \qlq_ld_active $15
+    assign \qlq_st_done 1'0
+    assign \qlq_st_done $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l"
-module \reset_l
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active"
+module \ld_active
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_reset
+  wire width 1 input 2 \r_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 3 \s_ld_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_reset
+  wire width 1 output 4 \q_ld_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -125322,7 +125422,7 @@ module \reset_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_reset
+    connect \A \r_ld_active
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -125348,7 +125448,7 @@ module \reset_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_reset
+    connect \B \s_ld_active
     connect \Y $5
   end
   process $group_0
@@ -125364,64 +125464,98 @@ module \reset_l
     sync posedge \coresync_clk
       update \q_int \q_int$next
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_ld_active
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_ld_active
+    connect \Y $11
+  end
   process $group_1
-    assign \q_reset 1'0
-    assign \q_reset \q_int
+    assign \q_ld_active 1'0
+    assign \q_ld_active $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_reset
+  wire width 1 \qn_ld_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $7
+  wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $8
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_reset
-    connect \Y $7
+    connect \A \q_ld_active
+    connect \Y $13
   end
   process $group_2
-    assign \qn_reset 1'0
-    assign \qn_reset $7
+    assign \qn_ld_active 1'0
+    assign \qn_ld_active $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_reset
+  wire width 1 \qlq_ld_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $9
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $10
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_reset
+    connect \A \q_ld_active
     connect \B \q_int
-    connect \Y $9
+    connect \Y $15
   end
   process $group_3
-    assign \qlq_reset 1'0
-    assign \qlq_reset $9
+    assign \qlq_ld_active 1'0
+    assign \qlq_ld_active $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l"
-module \adrok_l
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l"
+module \reset_l
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_addr_acked
+  wire width 1 input 2 \s_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 output 4 \qn_addr_acked
+  wire width 1 input 3 \r_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 5 \q_addr_acked
+  wire width 1 output 4 \q_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -125433,7 +125567,7 @@ module \adrok_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_addr_acked
+    connect \A \r_reset
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -125459,7 +125593,7 @@ module \adrok_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_addr_acked
+    connect \B \s_reset
     connect \Y $5
   end
   process $group_0
@@ -125475,96 +125609,64 @@ module \adrok_l
     sync posedge \coresync_clk
       update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_addr_acked
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_addr_acked
-    connect \Y $11
-  end
   process $group_1
-    assign \q_addr_acked 1'0
-    assign \q_addr_acked $11
+    assign \q_reset 1'0
+    assign \q_reset \q_int
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
+  wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_addr_acked
-    connect \Y $13
+    connect \A \q_reset
+    connect \Y $7
   end
   process $group_2
-    assign \qn_addr_acked 1'0
-    assign \qn_addr_acked $13
+    assign \qn_reset 1'0
+    assign \qn_reset $7
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_addr_acked
+  wire width 1 \qlq_reset
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
+  wire width 1 $9
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_addr_acked
+    connect \A \q_reset
     connect \B \q_int
-    connect \Y $15
+    connect \Y $9
   end
   process $group_3
-    assign \qlq_addr_acked 1'0
-    assign \qlq_addr_acked $15
+    assign \qlq_reset 1'0
+    assign \qlq_reset $9
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l"
-module \busy_l
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l"
+module \adrok_l
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_busy
+  wire width 1 input 2 \s_addr_acked
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_busy
+  wire width 1 input 3 \r_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 output 4 \qn_addr_acked
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_busy
+  wire width 1 output 5 \q_addr_acked
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -125576,7 +125678,7 @@ module \busy_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_busy
+    connect \A \r_addr_acked
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -125602,7 +125704,7 @@ module \busy_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_busy
+    connect \B \s_addr_acked
     connect \Y $5
   end
   process $group_0
@@ -125625,7 +125727,150 @@ module \busy_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_busy
+    connect \A \r_addr_acked
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_addr_acked
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_addr_acked 1'0
+    assign \q_addr_acked $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_addr_acked
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_addr_acked 1'0
+    assign \qn_addr_acked $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_addr_acked
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_addr_acked 1'0
+    assign \qlq_addr_acked $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l"
+module \busy_l
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_busy
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_busy
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_busy
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -125700,9 +125945,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l"
 module \cyc_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_cyc
@@ -125890,9 +126135,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l"
 module \valid_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_valid
@@ -126035,16 +126280,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.pimem"
 module \pimem
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 input 2 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 3 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 input 4 \ldst_port0_is_st_i
+  wire width 1 input 3 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 output 4 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 input 5 \ldst_port0_data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -126063,49 +126308,62 @@ module \pimem
   wire width 64 output 12 \ldst_port0_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 13 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 input 14 \x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 15 \ldst_port0_st_data_i_ok
+  wire width 1 input 14 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 16 \ldst_port0_st_data_i
+  wire width 64 input 15 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 17 \x_st_data_i
+  wire width 64 output 16 \x_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 18 \ldst_port0_addr_exc_o
+  wire width 1 input 17 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 19 \x_ld_i
+  wire width 1 output 18 \x_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 20 \x_st_i
+  wire width 1 output 19 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 input 20 \x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
   wire width 1 output 21 \m_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
   wire width 1 output 22 \x_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \st_active_r_st_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \st_active_s_st_active
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \st_active_q_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \st_active_r_st_active
   cell \st_active \st_active
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
+    connect \r_st_active \st_active_r_st_active
     connect \s_st_active \st_active_s_st_active
     connect \q_st_active \st_active_q_st_active
-    connect \r_st_active \st_active_r_st_active
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \ld_active_s_ld_active
+  wire width 1 \st_done_s_st_done
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \st_done_r_st_done
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \ld_active_q_ld_active
+  wire width 1 \st_done_q_st_done
+  cell \st_done \st_done
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_st_done \st_done_s_st_done
+    connect \r_st_done \st_done_r_st_done
+    connect \q_st_done \st_done_q_st_done
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \ld_active_r_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \ld_active_s_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \ld_active_q_ld_active
   cell \ld_active \ld_active
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
+    connect \r_ld_active \ld_active_r_ld_active
     connect \s_ld_active \ld_active_s_ld_active
     connect \q_ld_active \ld_active_q_ld_active
-    connect \r_ld_active \ld_active_r_ld_active
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \reset_l_s_reset
@@ -126184,6 +126442,8 @@ module \pimem
   wire width 1 \valid_l_q_valid
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \valid_l_r_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \valid_l_r_valid$next
   cell \valid_l \valid_l
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
@@ -126191,45 +126451,144 @@ module \pimem
     connect \q_valid \valid_l_q_valid
     connect \r_valid \valid_l_r_valid
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-  cell $or $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+  cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_st_data_i_ok
-    connect \B \ldst_port0_ld_data_o_ok
+    connect \A \st_active_q_st_active
+    connect \B \ldst_port0_st_data_i_ok
     connect \Y $1
   end
   process $group_0
+    assign \st_done_s_st_done 1'0
+    assign \st_done_s_st_done 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+      case 1'1
+        assign \st_done_s_st_done 1'1
+    end
+    sync init
+  end
+  process $group_1
+    assign \st_done_r_st_done 1'1
+    assign \st_done_r_st_done 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+      case 1'1
+        assign \st_done_r_st_done 1'1
+    end
+    sync init
+  end
+  process $group_2
+    assign \st_active_r_st_active 1'1
+    assign \st_active_r_st_active 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+      case 1'1
+        assign \st_active_r_st_active 1'1
+    end
+    sync init
+  end
+  process $group_3
+    assign \ld_active_r_ld_active 1'1
+    assign \ld_active_r_ld_active 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
+      case 1'1
+        assign \ld_active_r_ld_active 1'1
+    end
+    sync init
+  end
+  process $group_4
     assign \cyc_l_s_cyc 1'0
     assign \cyc_l_s_cyc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276"
+    switch { \reset_l_s_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276"
       case 1'1
         assign \cyc_l_s_cyc 1'1
     end
     sync init
   end
-  process $group_1
+  process $group_5
     assign \cyc_l_r_cyc 1'1
     assign \cyc_l_r_cyc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279"
     switch { \cyc_l_q_cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279"
       case 1'1
         assign \cyc_l_r_cyc 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200"
+  cell $or $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_ld_i
+    connect \B \ldst_port0_is_st_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:201"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+  wire width 1 \busy_delay
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+  wire width 1 \busy_delay$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:201"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \busy_delay
+    connect \Y $5
+  end
+  process $group_6
+    assign \busy_l_s_busy 1'0
+    assign \busy_l_s_busy 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200"
+      case 1'1
+        assign \busy_l_s_busy $5
+    end
+    sync init
+  end
+  process $group_7
+    assign \busy_l_r_busy 1'1
+    assign \busy_l_r_busy 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
+    switch { \ldst_port0_addr_exc_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271"
+      case 1'1
+        assign \busy_l_r_busy 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279"
+    switch { \cyc_l_q_cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279"
+      case 1'1
+        assign \busy_l_r_busy 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  cell $and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126237,33 +126596,33 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_addr_i_ok
     connect \B \adrok_l_qn_addr_acked
-    connect \Y $3
+    connect \Y $7
   end
-  process $group_2
+  process $group_8
     assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked
     assign \adrok_l_s_addr_acked$next 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $3 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+        switch { $7 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
           case 1'1
             assign \adrok_l_s_addr_acked$next 1'1
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
         switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
             switch { \adrok_l_qn_addr_acked }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
               case 1'1
                 assign \adrok_l_s_addr_acked$next 1'1
             end
@@ -126279,147 +126638,176 @@ module \pimem
     sync posedge \coresync_clk
       update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
   wire width 1 \reset_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
   wire width 1 \reset_delay$next
-  process $group_3
+  process $group_9
     assign \adrok_l_r_addr_acked 1'1
     assign \adrok_l_r_addr_acked 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
     switch { \reset_delay }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259"
       case 1'1
         assign \adrok_l_r_addr_acked 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
     switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
       case 1'1
         assign \adrok_l_r_addr_acked 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:176"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
   wire width 1 \lds
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
-  cell $and $6
+  process $group_10
+    assign \lds 1'0
+    assign \lds \ldst_port0_is_ld_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:184"
+  wire width 1 \sts
+  process $group_11
+    assign \sts 1'0
+    assign \sts \ldst_port0_is_st_i
+    sync init
+  end
+  process $group_12
+    assign \busy_delay$next \busy_delay
+    assign \busy_delay$next \ldst_port0_busy_o
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \busy_delay$next 1'0
+    end
+    sync init
+      update \busy_delay 1'0
+    sync posedge \coresync_clk
+      update \busy_delay \busy_delay$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:191"
+  wire width 1 \busy_edge
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193"
+  cell $not $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \busy_delay
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193"
+  cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_ld_i
-    connect \B \ldst_port0_busy_o
-    connect \Y $5
+    connect \A \ldst_port0_busy_o
+    connect \B $9
+    connect \Y $11
   end
-  process $group_4
-    assign \lds 1'0
-    assign \lds $5
+  process $group_13
+    assign \busy_edge 1'0
+    assign \busy_edge $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:177"
-  wire width 1 \sts
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
-  cell $and $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196"
+  cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_st_i
-    connect \B \ldst_port0_busy_o
-    connect \Y $7
-  end
-  process $group_5
-    assign \sts 1'0
-    assign \sts $7
-    sync init
+    connect \A \lds
+    connect \B \busy_edge
+    connect \Y $13
   end
-  process $group_6
+  process $group_14
     assign \ld_active_s_ld_active 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-    switch { \sts \lds }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-      case 2'-1
-        assign \ld_active_s_ld_active 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
-      case 2'1-
-    end
+    assign \ld_active_s_ld_active $13
     sync init
   end
-  process $group_7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197"
+  cell $and $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \sts
+    connect \B \busy_edge
+    connect \Y $15
+  end
+  process $group_15
     assign \st_active_s_st_active 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-    switch { \sts \lds }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-      case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
-      case 2'1-
-        assign \st_active_s_st_active 1'1
-    end
+    assign \st_active_s_st_active $15
     sync init
   end
-  process $group_8
+  process $group_16
     assign \lenexp_len_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
         assign \lenexp_len_i \ldst_port0_data_len
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
         assign \lenexp_len_i \ldst_port0_data_len
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  wire width 4 $9
+  wire width 4 $17
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  cell $pos $10
+  cell $pos $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A \ldst_port0_addr_i [2:0]
-    connect \Y $9
+    connect \Y $17
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  wire width 4 $11
+  wire width 4 $19
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  cell $pos $12
+  cell $pos $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A \ldst_port0_addr_i [2:0]
-    connect \Y $11
+    connect \Y $19
   end
-  process $group_9
+  process $group_17
     assign \lenexp_addr_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        assign \lenexp_addr_i $9
+        assign \lenexp_addr_i $17
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        assign \lenexp_addr_i $11
+        assign \lenexp_addr_i $19
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126427,38 +126815,38 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_addr_i_ok
     connect \B \adrok_l_qn_addr_acked
-    connect \Y $13
+    connect \Y $21
   end
-  process $group_10
+  process $group_18
     assign \valid_l_s_valid 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+        switch { $21 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
           case 1'1
             assign \valid_l_s_valid 1'1
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
         switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
           case 1'1
             assign \valid_l_s_valid 1'1
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  cell $and $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126466,38 +126854,38 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_addr_i_ok
     connect \B \adrok_l_qn_addr_acked
-    connect \Y $15
+    connect \Y $23
   end
-  process $group_11
+  process $group_19
     assign \x_mask_i 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $15 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+        switch { $23 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
           case 1'1
             assign \x_mask_i \lenexp_lexp_o [7:0]
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
         switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
           case 1'1
             assign \x_mask_i \lenexp_lexp_o [7:0]
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  cell $and $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126505,38 +126893,38 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_addr_i_ok
     connect \B \adrok_l_qn_addr_acked
-    connect \Y $17
+    connect \Y $25
   end
-  process $group_12
+  process $group_20
     assign \x_addr_i 48'000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $17 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+        switch { $25 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
           case 1'1
             assign \x_addr_i \ldst_port0_addr_i
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
         switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
           case 1'1
             assign \x_addr_i \ldst_port0_addr_i
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+  cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126544,32 +126932,32 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_addr_i_ok
     connect \B \adrok_l_qn_addr_acked
-    connect \Y $19
+    connect \Y $27
   end
-  process $group_13
+  process $group_21
     assign \ldst_port0_addr_ok_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
     switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
+        switch { $27 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210"
           case 1'1
             assign \ldst_port0_addr_ok_o 1'1
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
     switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
         switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
             switch { \adrok_l_qn_addr_acked }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224"
               case 1'1
                 assign \ldst_port0_addr_ok_o 1'1
             end
@@ -126577,10 +126965,10 @@ module \pimem
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  cell $and $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126588,77 +126976,66 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ld_active_q_ld_active
     connect \B \adrok_l_q_addr_acked
-    connect \Y $21
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  cell $not $24
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_busy_o
-    connect \Y $23
+    connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:44"
+  wire width 1 \lsui_busy
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62"
+  cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st_active_q_st_active
-    connect \B \ldst_port0_st_data_i_ok
-    connect \Y $25
+    connect \A \lsui_busy
+    connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
-  cell $not $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:59"
+  wire width 1 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:59"
+  cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \x_busy_o
-    connect \Y $27
+    connect \A \lsui_busy
+    connect \Y $33
   end
-  process $group_14
+  process $group_22
     assign \reset_l_s_reset 1'0
     assign \reset_l_s_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $21 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+    switch { $29 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
       case 1'1
-        assign \reset_l_s_reset $23
+        assign \reset_l_s_reset $31
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $25 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+    switch { \st_done_q_st_done }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
       case 1'1
-        assign \reset_l_s_reset $27
+        assign \reset_l_s_reset $33
     end
     sync init
   end
-  process $group_15
+  process $group_23
     assign \reset_l_r_reset 1'1
     assign \reset_l_r_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
     switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263"
       case 1'1
         assign \reset_l_r_reset 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232"
   wire width 64 \lddata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 176 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
-  wire width 176 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
-  cell $and $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235"
+  wire width 176 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234"
+  wire width 176 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234"
+  cell $and $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -126666,12 +127043,12 @@ module \pimem
     parameter \Y_WIDTH 176
     connect \A \m_ld_data_o
     connect \B \lenexp_rexp_o
-    connect \Y $30
+    connect \Y $36
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 8 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  cell $mul $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235"
+  wire width 8 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235"
+  cell $mul $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -126679,31 +127056,31 @@ module \pimem
     parameter \Y_WIDTH 8
     connect \A \lenexp_addr_i
     connect \B 4'1000
-    connect \Y $32
+    connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 176 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  cell $sshr $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235"
+  wire width 176 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235"
+  cell $sshr $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 176
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 176
-    connect \A $30
-    connect \B $32
-    connect \Y $34
+    connect \A $36
+    connect \B $38
+    connect \Y $40
   end
-  connect $29 $34
-  process $group_16
+  connect $35 $40
+  process $group_24
     assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \lddata $29 [63:0]
+    assign \lddata $35 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  wire width 1 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  cell $and $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126711,22 +127088,22 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ld_active_q_ld_active
     connect \B \adrok_l_q_addr_acked
-    connect \Y $36
+    connect \Y $42
   end
-  process $group_17
+  process $group_25
     assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $36 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+    switch { $42 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
       case 1'1
         assign \ldst_port0_ld_data_o \lddata
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+  cell $and $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126734,34 +127111,34 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ld_active_q_ld_active
     connect \B \adrok_l_q_addr_acked
-    connect \Y $38
+    connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  cell $not $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62"
+  wire width 1 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62"
+  cell $not $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \x_busy_o
-    connect \Y $40
+    connect \A \lsui_busy
+    connect \Y $46
   end
-  process $group_18
+  process $group_26
     assign \ldst_port0_ld_data_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $38 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
+    switch { $44 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236"
       case 1'1
-        assign \ldst_port0_ld_data_o_ok $40
+        assign \ldst_port0_ld_data_o_ok $46
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247"
   wire width 64 \stdata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+  wire width 1 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+  cell $and $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126769,14 +127146,14 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \st_active_q_st_active
     connect \B \ldst_port0_st_data_i_ok
-    connect \Y $42
+    connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 319 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 8 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  cell $mul $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248"
+  wire width 319 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248"
+  wire width 8 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248"
+  cell $mul $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
@@ -126784,36 +127161,36 @@ module \pimem
     parameter \Y_WIDTH 8
     connect \A \lenexp_addr_i
     connect \B 4'1000
-    connect \Y $45
+    connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 319 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  cell $sshl $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248"
+  wire width 319 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248"
+  cell $sshl $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 319
     connect \A \ldst_port0_st_data_i
-    connect \B $45
-    connect \Y $47
+    connect \B $51
+    connect \Y $53
   end
-  connect $44 $47
-  process $group_19
+  connect $50 $53
+  process $group_27
     assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $42 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+    switch { $48 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
       case 1'1
-        assign \stdata $44 [63:0]
+        assign \stdata $50 [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+  cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126821,19 +127198,19 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \st_active_q_st_active
     connect \B \ldst_port0_st_data_i_ok
-    connect \Y $49
+    connect \Y $55
   end
-  process $group_20
+  process $group_28
     assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $49 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
+    switch { $55 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244"
       case 1'1
         assign \x_st_data_i \stdata
     end
     sync init
   end
-  process $group_21
+  process $group_29
     assign \reset_delay$next \reset_delay
     assign \reset_delay$next \reset_l_q_reset
     sync init
@@ -126841,30 +127218,29 @@ module \pimem
     sync posedge \coresync_clk
       update \reset_delay \reset_delay$next
   end
-  process $group_22
-    assign \ld_active_r_ld_active 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \ld_active_r_ld_active 1'1
-    end
+  process $group_30
+    assign \ldst_port0_busy_o 1'0
+    assign \ldst_port0_busy_o \busy_l_q_busy
     sync init
   end
-  process $group_23
-    assign \st_active_r_st_active 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \st_active_r_st_active 1'1
-    end
+  process $group_31
+    assign \x_ld_i 1'0
+    assign \x_ld_i \ldst_port0_is_ld_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-  cell $or $52
+  process $group_32
+    assign \x_st_i 1'0
+    assign \x_st_i \ldst_port0_is_st_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83"
+  wire width 2 \fsm_state
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83"
+  wire width 2 \fsm_state$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -126872,81 +127248,198 @@ module \pimem
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_is_ld_i
     connect \B \ldst_port0_is_st_i
-    connect \Y $51
+    connect \Y $57
   end
-  process $group_24
-    assign \busy_l_s_busy 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-    switch { $51 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-      case 1'1
-        assign \busy_l_s_busy 1'1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  cell $and $60
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $57
+    connect \B \valid_l_q_valid
+    connect \Y $59
+  end
+  process $group_33
+    assign \lsui_busy 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83"
+    switch \fsm_state
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:84"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+        switch { $59 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+          case 1'1
+            assign \lsui_busy 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:89"
+      attribute \nmigen.decoding "BUSY/1"
+      case 2'01
+        assign \lsui_busy 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
+      attribute \nmigen.decoding "WAITDEASSERT/2"
+      case 2'10
     end
     sync init
   end
-  process $group_25
-    assign \busy_l_r_busy 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
-    switch { \ldst_port0_addr_exc_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
-      case 1'1
-        assign \busy_l_r_busy 1'1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  wire width 1 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  cell $or $62
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_ld_i
+    connect \B \ldst_port0_is_st_i
+    connect \Y $61
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  wire width 1 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+  cell $and $64
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $61
+    connect \B \valid_l_q_valid
+    connect \Y $63
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93"
+  wire width 1 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93"
+  cell $not $66
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_busy_o
+    connect \Y $65
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97"
+  wire width 1 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97"
+  cell $not $68
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \valid_l_q_valid
+    connect \Y $67
+  end
+  process $group_34
+    assign \fsm_state$next \fsm_state
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83"
+    switch \fsm_state
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:84"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+        switch { $63 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86"
+          case 1'1
+            assign \fsm_state$next 2'01
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:89"
+      attribute \nmigen.decoding "BUSY/1"
+      case 2'01
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93"
+        switch { $65 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93"
+          case 1'1
+            assign \fsm_state$next 2'10
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95"
+      attribute \nmigen.decoding "WAITDEASSERT/2"
+      case 2'10
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97"
+        switch { $67 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97"
+          case 1'1
+            assign \fsm_state$next 2'00
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
-    switch { \cyc_l_q_cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \busy_l_r_busy 1'1
+        assign \fsm_state$next 2'00
     end
     sync init
+      update \fsm_state 2'00
+    sync posedge \coresync_clk
+      update \fsm_state \fsm_state$next
   end
-  process $group_26
-    assign \ldst_port0_busy_o 1'0
-    assign \ldst_port0_busy_o \busy_l_q_busy
-    sync init
-  end
-  process $group_27
-    assign \x_ld_i 1'0
-    assign \x_ld_i \ldst_port0_is_ld_i
-    sync init
-  end
-  process $group_28
-    assign \x_st_i 1'0
-    assign \x_st_i \ldst_port0_is_st_i
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:101"
+  wire width 1 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:101"
+  cell $or $70
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \valid_l_q_valid
+    connect \B \lsui_busy
+    connect \Y $69
   end
-  process $group_29
+  process $group_35
     assign \m_valid_i 1'0
-    assign \m_valid_i \valid_l_q_valid
+    assign \m_valid_i $69
     sync init
   end
-  process $group_30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:102"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:102"
+  cell $or $72
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \valid_l_q_valid
+    connect \B \lsui_busy
+    connect \Y $71
+  end
+  process $group_36
     assign \x_valid_i 1'0
-    assign \x_valid_i \valid_l_q_valid
+    assign \x_valid_i $71
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
-  cell $not $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:105"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:105"
+  cell $not $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_busy_o
-    connect \Y $53
+    connect \A \lsui_busy
+    connect \Y $73
   end
-  process $group_31
-    assign \valid_l_r_valid 1'1
-    assign \valid_l_r_valid $53
+  process $group_37
+    assign \valid_l_r_valid$next \valid_l_r_valid
+    assign \valid_l_r_valid$next $73
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \valid_l_r_valid$next 1'1
+    end
     sync init
+      update \valid_l_r_valid 1'1
+    sync posedge \coresync_clk
+      update \valid_l_r_valid \valid_l_r_valid$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l"
 module \idx_l
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_idx_l
@@ -127089,9 +127582,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l"
 module \reset_l$124
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_reset
@@ -127236,9 +127729,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.l0"
 module \l0$123
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 input 2 \ldst_port0_is_ld_i
@@ -127264,10 +127757,10 @@ module \l0$123
   wire width 1 input 12 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 13 \ldst_port0_is_ld_i$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 input 14 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 15 \ldst_port0_is_st_i$2
+  wire width 1 output 14 \ldst_port0_is_st_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 input 15 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 16 \ldst_port0_data_len$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -127632,9 +128125,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem"
 module \lsmem
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
   wire width 8 input 2 \x_mask_i
@@ -127644,14 +128137,14 @@ module \lsmem
   wire width 64 output 4 \m_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
   wire width 64 \m_ld_data_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 5 \x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 input 6 \x_st_data_i
+  wire width 64 input 5 \x_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 input 7 \x_ld_i
+  wire width 1 input 6 \x_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 input 8 \x_st_i
+  wire width 1 input 7 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 output 8 \x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
   wire width 1 input 9 \m_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
@@ -127669,15 +128162,15 @@ module \lsmem
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 \dbus__stb$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 15 \dbus__dat_r
+  wire width 8 output 15 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 16 \dbus__adr
+  wire width 8 \dbus__sel$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 \dbus__adr$next
+  wire width 64 input 16 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 17 \dbus__sel
+  wire width 45 output 17 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 \dbus__sel$next
+  wire width 45 \dbus__adr$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 18 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
@@ -127686,9 +128179,9 @@ module \lsmem
   wire width 64 output 19 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 64 \dbus__dat_w$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $or $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127699,9 +128192,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127712,11 +128205,11 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
   wire width 1 \x_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127724,9 +128217,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127785,10 +128278,10 @@ module \lsmem
           case 1'1
             assign \dbus__cyc$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
         assign \dbus__cyc$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -127801,9 +128294,9 @@ module \lsmem
     sync posedge \coresync_clk
       update \dbus__cyc \dbus__cyc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127814,9 +128307,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127827,9 +128320,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127837,9 +128330,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127898,10 +128391,10 @@ module \lsmem
           case 1'1
             assign \dbus__stb$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
         assign \dbus__stb$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -127914,9 +128407,9 @@ module \lsmem
     sync posedge \coresync_clk
       update \dbus__stb \dbus__stb$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $or $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127927,9 +128420,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127940,9 +128433,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -127950,9 +128443,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -128000,7 +128493,7 @@ module \lsmem
     connect \Y $41
   end
   process $group_2
-    assign \m_ld_data_o$next \m_ld_data_o
+    assign \dbus__sel$next \dbus__sel
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $35 \dbus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
@@ -128009,26 +128502,29 @@ module \lsmem
         switch { $41 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
           case 1'1
-            assign \m_ld_data_o$next \dbus__dat_r
+            assign \dbus__sel$next 8'00000000
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+        assign \dbus__sel$next \x_mask_i
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
+        assign \dbus__sel$next 8'00000000
+        assign \dbus__sel$next 8'00000000
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
-        assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dbus__sel$next 8'00000000
     end
     sync init
-      update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \dbus__sel 8'00000000
     sync posedge \coresync_clk
-      update \m_ld_data_o \m_ld_data_o$next
+      update \dbus__sel \dbus__sel$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $or $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -128039,9 +128535,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -128052,9 +128548,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $not $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -128062,9 +128558,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
   cell $and $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -128075,33 +128571,73 @@ module \lsmem
     connect \B $47
     connect \Y $49
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $52
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__ack
+    connect \B \dbus__err
+    connect \Y $51
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $not $54
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_valid_i
+    connect \Y $53
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $56
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $51
+    connect \B $53
+    connect \Y $55
+  end
   process $group_3
-    assign \dbus__adr$next \dbus__adr
+    assign \m_ld_data_o$next \m_ld_data_o
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $49 \dbus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+        switch { $55 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+          case 1'1
+            assign \m_ld_data_o$next \dbus__dat_r
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
-        assign \dbus__adr$next \x_addr_i [47:3]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
-        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
-        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+        assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
-      update \dbus__adr 45'000000000000000000000000000000000000000000000
+      update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     sync posedge \coresync_clk
-      update \dbus__adr \dbus__adr$next
+      update \m_ld_data_o \m_ld_data_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128109,72 +128645,71 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \x_ld_i
     connect \B \x_st_i
-    connect \Y $51
+    connect \Y $57
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $51
+    connect \A $57
     connect \B \x_valid_i
-    connect \Y $53
+    connect \Y $59
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $not $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \x_stall_i
-    connect \Y $55
+    connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $53
-    connect \B $55
-    connect \Y $57
+    connect \A $59
+    connect \B $61
+    connect \Y $63
   end
   process $group_4
-    assign \dbus__sel$next \dbus__sel
+    assign \dbus__adr$next \dbus__adr
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $57 \dbus__cyc }
+    switch { $63 \dbus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
-        assign \dbus__sel$next \x_mask_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+        assign \dbus__adr$next \x_addr_i [47:3]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
-        assign \dbus__sel$next 8'00000000
-        assign \dbus__sel$next 8'00000000
+        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
-        assign \dbus__sel$next 8'00000000
+        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
     end
     sync init
-      update \dbus__sel 8'00000000
+      update \dbus__adr 45'000000000000000000000000000000000000000000000
     sync posedge \coresync_clk
-      update \dbus__sel \dbus__sel$next
+      update \dbus__adr \dbus__adr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $or $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128182,54 +128717,54 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \x_ld_i
     connect \B \x_st_i
-    connect \Y $59
+    connect \Y $65
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $59
+    connect \A $65
     connect \B \x_valid_i
-    connect \Y $61
+    connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $not $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \x_stall_i
-    connect \Y $63
+    connect \Y $69
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $61
-    connect \B $63
-    connect \Y $65
+    connect \A $67
+    connect \B $69
+    connect \Y $71
   end
   process $group_5
     assign \dbus__we$next \dbus__we
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $65 \dbus__cyc }
+    switch { $71 \dbus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
         assign \dbus__we$next \x_st_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
         assign \dbus__we$next 1'0
     end
@@ -128243,10 +128778,10 @@ module \lsmem
     sync posedge \coresync_clk
       update \dbus__we \dbus__we$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $or $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128254,54 +128789,54 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \x_ld_i
     connect \B \x_st_i
-    connect \Y $67
+    connect \Y $73
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $67
+    connect \A $73
     connect \B \x_valid_i
-    connect \Y $69
+    connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $not $78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \x_stall_i
-    connect \Y $71
+    connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  wire width 1 $79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
+  cell $and $80
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $69
-    connect \B $71
-    connect \Y $73
+    connect \A $75
+    connect \B $77
+    connect \Y $79
   end
   process $group_6
     assign \dbus__dat_w$next \dbus__dat_w
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $73 \dbus__cyc }
+    switch { $79 \dbus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92"
       case 2'1-
         assign \dbus__dat_w$next \x_st_data_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101"
       case
         assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
@@ -128319,10 +128854,10 @@ module \lsmem
   wire width 1 \m_load_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
   wire width 1 \m_load_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  wire width 1 $81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  cell $and $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128330,38 +128865,38 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \dbus__cyc
     connect \B \dbus__err
-    connect \Y $75
+    connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  wire width 1 $83
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
   wire width 1 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  cell $not $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \m_stall_i
-    connect \Y $77
+    connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
-  wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
-  cell $not $80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:112"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:112"
+  cell $not $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbus__we
-    connect \Y $79
+    connect \Y $85
   end
   process $group_7
     assign \m_load_err_o$next \m_load_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $77 $75 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+    switch { $83 $81 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
       case 2'-1
-        assign \m_load_err_o$next $79
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+        assign \m_load_err_o$next $85
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
       case 2'1-
         assign \m_load_err_o$next 1'0
     end
@@ -128379,10 +128914,10 @@ module \lsmem
   wire width 1 \m_store_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
   wire width 1 \m_store_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  wire width 1 $87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  cell $and $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128390,26 +128925,26 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \dbus__cyc
     connect \B \dbus__err
-    connect \Y $81
+    connect \Y $87
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  wire width 1 $89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  cell $not $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \m_stall_i
-    connect \Y $83
+    connect \Y $89
   end
   process $group_8
     assign \m_store_err_o$next \m_store_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $83 $81 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+    switch { $89 $87 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
       case 2'-1
         assign \m_store_err_o$next \dbus__we
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
       case 2'1-
         assign \m_store_err_o$next 1'0
     end
@@ -128427,10 +128962,10 @@ module \lsmem
   wire width 45 \m_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 \m_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  wire width 1 $91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128438,26 +128973,26 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \dbus__cyc
     connect \B \dbus__err
-    connect \Y $85
+    connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  wire width 1 $93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
+  cell $not $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \m_stall_i
-    connect \Y $87
+    connect \Y $93
   end
   process $group_9
     assign \m_badaddr_o$next \m_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $87 $85 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+    switch { $93 $91 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
       case 2'-1
         assign \m_badaddr_o$next \dbus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116"
       case 2'1-
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -128477,10 +129012,10 @@ module \lsmem
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
   wire width 1 \m_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-  wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-  cell $or $90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
+  wire width 1 $95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
+  cell $or $96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -128488,16 +129023,16 @@ module \lsmem
     parameter \Y_WIDTH 1
     connect \A \m_load_err_o
     connect \B \m_store_err_o
-    connect \Y $89
+    connect \Y $95
   end
   process $group_11
     assign \m_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-    switch { $89 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
+    switch { $95 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
       case 1'1
         assign \m_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:125"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:126"
       case
         assign \m_busy_o \dbus__cyc
     end
@@ -128509,9 +129044,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0"
 module \l0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 input 2 \ldst_port0_is_ld_i
@@ -128544,21 +129079,21 @@ module \l0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 16 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 17 \dbus__dat_r
+  wire width 8 output 17 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 18 \dbus__adr
+  wire width 64 input 18 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 19 \dbus__sel
+  wire width 45 output 19 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 20 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 64 output 21 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 \pimem_ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 \pimem_ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
   wire width 1 \pimem_ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 \pimem_ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 \pimem_ldst_port0_data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -128577,8 +129112,6 @@ module \l0
   wire width 64 \pimem_ldst_port0_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pimem_ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 \pimem_x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pimem_ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -128591,6 +129124,8 @@ module \l0
   wire width 1 \pimem_x_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
   wire width 1 \pimem_x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 \pimem_x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
   wire width 1 \pimem_m_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
@@ -128599,8 +129134,8 @@ module \l0
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i
-    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
     connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
     connect \ldst_port0_data_len \pimem_ldst_port0_data_len
     connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
     connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
@@ -128610,13 +129145,13 @@ module \l0
     connect \m_ld_data_o \pimem_m_ld_data_o
     connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
     connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
-    connect \x_busy_o \pimem_x_busy_o
     connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
     connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
     connect \x_st_data_i \pimem_x_st_data_i
     connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
     connect \x_ld_i \pimem_x_ld_i
     connect \x_st_i \pimem_x_st_i
+    connect \x_busy_o \pimem_x_busy_o
     connect \m_valid_i \pimem_m_valid_i
     connect \x_valid_i \pimem_x_valid_i
   end
@@ -128635,8 +129170,8 @@ module \l0
     connect \ldst_port0_st_data_i \ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
     connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i
-    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
     connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
     connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len
     connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i
     connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok
@@ -128653,19 +129188,19 @@ module \l0
     connect \x_mask_i \pimem_x_mask_i
     connect \x_addr_i \pimem_x_addr_i
     connect \m_ld_data_o \pimem_m_ld_data_o
-    connect \x_busy_o \pimem_x_busy_o
     connect \x_st_data_i \pimem_x_st_data_i
     connect \x_ld_i \pimem_x_ld_i
     connect \x_st_i \pimem_x_st_i
+    connect \x_busy_o \pimem_x_busy_o
     connect \m_valid_i \pimem_m_valid_i
     connect \x_valid_i \pimem_x_valid_i
     connect \dbus__cyc \dbus__cyc
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
     connect \dbus__stb \dbus__stb
+    connect \dbus__sel \dbus__sel
     connect \dbus__dat_r \dbus__dat_r
     connect \dbus__adr \dbus__adr
-    connect \dbus__sel \dbus__sel
     connect \dbus__we \dbus__we
     connect \dbus__dat_w \dbus__dat_w
   end
@@ -128674,34 +129209,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
 module \reg_0
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src10__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src20__ren
+  wire width 1 input 4 \src30__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src20__data_o
+  wire width 64 output 5 \src30__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src30__ren
+  wire width 1 input 6 \dmi0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src30__data_o
+  wire width 64 output 7 \dmi0__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi0__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi0__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest10__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest10__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest20__wen
+  wire width 1 input 8 \dest10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest20__data_i
+  wire width 64 input 9 \dest10__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -128730,12 +129257,6 @@ module \reg_0
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -128780,12 +129301,6 @@ module \reg_0
           case 1'1
             assign \src10__data_o \dest10__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest20__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -128809,7 +129324,7 @@ module \reg_0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src20__ren
+    connect \A \src30__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -128826,12 +129341,6 @@ module \reg_0
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -128846,7 +129355,7 @@ module \reg_0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src20__ren
+    connect \A \src30__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -128861,7 +129370,7 @@ module \reg_0
     connect \Y $12
   end
   process $group_3
-    assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -128870,23 +129379,17 @@ module \reg_0
         switch { \dest10__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src20__data_o \dest10__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest20__data_i
+            assign \src30__data_o \dest10__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src20__data_o \reg
+            assign \src30__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -128901,7 +129404,7 @@ module \reg_0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src30__ren
+    connect \A \dmi0__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -128918,12 +129421,6 @@ module \reg_0
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -128938,7 +129435,7 @@ module \reg_0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src30__ren
+    connect \A \dmi0__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -128953,101 +129450,9 @@ module \reg_0
     connect \Y $19
   end
   process $group_5
-    assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src30__data_o \dest10__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src30__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src30__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi0__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi0__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -129056,14 +129461,8 @@ module \reg_0
           case 1'1
             assign \dmi0__data_o \dest10__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi0__data_o \dest20__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi0__data_o \reg
@@ -129074,7 +129473,7 @@ module \reg_0
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest10__wen }
@@ -129082,12 +129481,6 @@ module \reg_0
       case 1'1
         assign \reg$next \dest10__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest20__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest20__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -129102,34 +129495,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_1"
 module \reg_1
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src11__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src11__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src21__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src21__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src31__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src31__data_o
+  wire width 1 input 4 \src31__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi1__ren
+  wire width 64 output 5 \src31__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi1__data_o
+  wire width 1 input 6 \dmi1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest11__wen
+  wire width 64 output 7 \dmi1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest11__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest21__wen
+  wire width 1 input 8 \dest11__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest21__data_i
+  wire width 64 input 9 \dest11__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -129158,12 +129543,6 @@ module \reg_1
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129208,12 +129587,6 @@ module \reg_1
           case 1'1
             assign \src11__data_o \dest11__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src11__data_o \dest21__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -129237,7 +129610,7 @@ module \reg_1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
+    connect \A \src31__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -129254,12 +129627,6 @@ module \reg_1
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129274,7 +129641,7 @@ module \reg_1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
+    connect \A \src31__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -129289,7 +129656,7 @@ module \reg_1
     connect \Y $12
   end
   process $group_3
-    assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -129298,23 +129665,17 @@ module \reg_1
         switch { \dest11__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src21__data_o \dest11__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src21__data_o \dest21__data_i
+            assign \src31__data_o \dest11__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src21__data_o \reg
+            assign \src31__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -129329,7 +129690,7 @@ module \reg_1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src31__ren
+    connect \A \dmi1__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -129346,12 +129707,6 @@ module \reg_1
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129366,7 +129721,7 @@ module \reg_1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src31__ren
+    connect \A \dmi1__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -129381,101 +129736,9 @@ module \reg_1
     connect \Y $19
   end
   process $group_5
-    assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src31__data_o \dest11__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src31__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src31__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi1__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi1__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -129484,14 +129747,8 @@ module \reg_1
           case 1'1
             assign \dmi1__data_o \dest11__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi1__data_o \dest21__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi1__data_o \reg
@@ -129502,7 +129759,7 @@ module \reg_1
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest11__wen }
@@ -129510,12 +129767,6 @@ module \reg_1
       case 1'1
         assign \reg$next \dest11__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest21__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest21__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -129530,34 +129781,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_2"
 module \reg_2
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src12__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src12__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src22__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src22__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src32__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src32__data_o
+  wire width 1 input 4 \src32__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi2__ren
+  wire width 64 output 5 \src32__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi2__data_o
+  wire width 1 input 6 \dmi2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest12__wen
+  wire width 64 output 7 \dmi2__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest12__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest22__wen
+  wire width 1 input 8 \dest12__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest22__data_i
+  wire width 64 input 9 \dest12__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -129586,12 +129829,6 @@ module \reg_2
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129636,12 +129873,6 @@ module \reg_2
           case 1'1
             assign \src12__data_o \dest12__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest22__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -129665,7 +129896,7 @@ module \reg_2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
+    connect \A \src32__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -129682,12 +129913,6 @@ module \reg_2
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129702,7 +129927,7 @@ module \reg_2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
+    connect \A \src32__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -129717,7 +129942,7 @@ module \reg_2
     connect \Y $12
   end
   process $group_3
-    assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -129726,23 +129951,17 @@ module \reg_2
         switch { \dest12__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src22__data_o \dest12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest22__data_i
+            assign \src32__data_o \dest12__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src22__data_o \reg
+            assign \src32__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -129757,7 +129976,7 @@ module \reg_2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src32__ren
+    connect \A \dmi2__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -129774,12 +129993,6 @@ module \reg_2
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -129794,7 +130007,7 @@ module \reg_2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src32__ren
+    connect \A \dmi2__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -129809,101 +130022,9 @@ module \reg_2
     connect \Y $19
   end
   process $group_5
-    assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src32__data_o \dest12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src32__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src32__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi2__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi2__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -129912,14 +130033,8 @@ module \reg_2
           case 1'1
             assign \dmi2__data_o \dest12__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi2__data_o \dest22__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi2__data_o \reg
@@ -129930,7 +130045,7 @@ module \reg_2
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest12__wen }
@@ -129938,12 +130053,6 @@ module \reg_2
       case 1'1
         assign \reg$next \dest12__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest22__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest22__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -129958,34 +130067,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_3"
 module \reg_3
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src13__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src13__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src33__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src33__data_o
+  wire width 1 input 4 \src33__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi3__ren
+  wire width 64 output 5 \src33__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi3__data_o
+  wire width 1 input 6 \dmi3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest13__wen
+  wire width 64 output 7 \dmi3__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest13__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest23__wen
+  wire width 1 input 8 \dest13__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest23__data_i
+  wire width 64 input 9 \dest13__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -130014,12 +130115,6 @@ module \reg_3
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130064,12 +130159,6 @@ module \reg_3
           case 1'1
             assign \src13__data_o \dest13__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest23__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -130093,7 +130182,7 @@ module \reg_3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
+    connect \A \src33__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -130110,12 +130199,6 @@ module \reg_3
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130130,7 +130213,7 @@ module \reg_3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
+    connect \A \src33__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -130145,7 +130228,7 @@ module \reg_3
     connect \Y $12
   end
   process $group_3
-    assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -130154,23 +130237,17 @@ module \reg_3
         switch { \dest13__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src23__data_o \dest13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest23__data_i
+            assign \src33__data_o \dest13__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src23__data_o \reg
+            assign \src33__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -130185,7 +130262,7 @@ module \reg_3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src33__ren
+    connect \A \dmi3__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -130202,12 +130279,6 @@ module \reg_3
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130222,7 +130293,7 @@ module \reg_3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src33__ren
+    connect \A \dmi3__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -130237,101 +130308,9 @@ module \reg_3
     connect \Y $19
   end
   process $group_5
-    assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src33__data_o \dest13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src33__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src33__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi3__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi3__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -130340,14 +130319,8 @@ module \reg_3
           case 1'1
             assign \dmi3__data_o \dest13__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi3__data_o \dest23__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi3__data_o \reg
@@ -130358,7 +130331,7 @@ module \reg_3
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest13__wen }
@@ -130366,12 +130339,6 @@ module \reg_3
       case 1'1
         assign \reg$next \dest13__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest23__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest23__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -130386,34 +130353,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_4"
 module \reg_4
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src14__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src14__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src24__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src24__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src34__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src34__data_o
+  wire width 1 input 4 \src34__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi4__ren
+  wire width 64 output 5 \src34__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi4__data_o
+  wire width 1 input 6 \dmi4__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest14__wen
+  wire width 64 output 7 \dmi4__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest14__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest24__wen
+  wire width 1 input 8 \dest14__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest24__data_i
+  wire width 64 input 9 \dest14__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -130442,12 +130401,6 @@ module \reg_4
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130492,12 +130445,6 @@ module \reg_4
           case 1'1
             assign \src14__data_o \dest14__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest24__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -130521,7 +130468,7 @@ module \reg_4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
+    connect \A \src34__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -130538,12 +130485,6 @@ module \reg_4
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130558,7 +130499,7 @@ module \reg_4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
+    connect \A \src34__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -130573,7 +130514,7 @@ module \reg_4
     connect \Y $12
   end
   process $group_3
-    assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -130582,23 +130523,17 @@ module \reg_4
         switch { \dest14__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src24__data_o \dest14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest24__data_i
+            assign \src34__data_o \dest14__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src24__data_o \reg
+            assign \src34__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -130613,7 +130548,7 @@ module \reg_4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src34__ren
+    connect \A \dmi4__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -130630,12 +130565,6 @@ module \reg_4
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130650,7 +130579,7 @@ module \reg_4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src34__ren
+    connect \A \dmi4__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -130665,101 +130594,9 @@ module \reg_4
     connect \Y $19
   end
   process $group_5
-    assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src34__data_o \dest14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src34__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src34__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi4__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi4__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -130768,14 +130605,8 @@ module \reg_4
           case 1'1
             assign \dmi4__data_o \dest14__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi4__data_o \dest24__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi4__data_o \reg
@@ -130786,7 +130617,7 @@ module \reg_4
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest14__wen }
@@ -130794,12 +130625,6 @@ module \reg_4
       case 1'1
         assign \reg$next \dest14__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest24__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest24__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -130814,34 +130639,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_5"
 module \reg_5
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src15__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src15__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src25__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src25__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src35__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src35__data_o
+  wire width 1 input 4 \src35__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi5__ren
+  wire width 64 output 5 \src35__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi5__data_o
+  wire width 1 input 6 \dmi5__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest15__wen
+  wire width 64 output 7 \dmi5__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest15__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest25__wen
+  wire width 1 input 8 \dest15__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest25__data_i
+  wire width 64 input 9 \dest15__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -130870,12 +130687,6 @@ module \reg_5
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130920,12 +130731,6 @@ module \reg_5
           case 1'1
             assign \src15__data_o \dest15__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest25__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -130949,7 +130754,7 @@ module \reg_5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
+    connect \A \src35__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -130966,12 +130771,6 @@ module \reg_5
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -130986,7 +130785,7 @@ module \reg_5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
+    connect \A \src35__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -131001,7 +130800,7 @@ module \reg_5
     connect \Y $12
   end
   process $group_3
-    assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131010,23 +130809,17 @@ module \reg_5
         switch { \dest15__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src25__data_o \dest15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest25__data_i
+            assign \src35__data_o \dest15__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src25__data_o \reg
+            assign \src35__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -131041,7 +130834,7 @@ module \reg_5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src35__ren
+    connect \A \dmi5__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -131058,12 +130851,6 @@ module \reg_5
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131078,7 +130865,7 @@ module \reg_5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src35__ren
+    connect \A \dmi5__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -131093,101 +130880,9 @@ module \reg_5
     connect \Y $19
   end
   process $group_5
-    assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src35__data_o \dest15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src35__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src35__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi5__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi5__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -131196,14 +130891,8 @@ module \reg_5
           case 1'1
             assign \dmi5__data_o \dest15__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi5__data_o \dest25__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi5__data_o \reg
@@ -131214,7 +130903,7 @@ module \reg_5
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest15__wen }
@@ -131222,12 +130911,6 @@ module \reg_5
       case 1'1
         assign \reg$next \dest15__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest25__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest25__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -131242,34 +130925,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_6"
 module \reg_6
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src16__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src16__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src36__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src36__data_o
+  wire width 1 input 4 \src36__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi6__ren
+  wire width 64 output 5 \src36__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi6__data_o
+  wire width 1 input 6 \dmi6__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest16__wen
+  wire width 64 output 7 \dmi6__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest16__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest26__wen
+  wire width 1 input 8 \dest16__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest26__data_i
+  wire width 64 input 9 \dest16__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131298,12 +130973,6 @@ module \reg_6
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131348,12 +131017,6 @@ module \reg_6
           case 1'1
             assign \src16__data_o \dest16__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest26__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -131377,7 +131040,7 @@ module \reg_6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
+    connect \A \src36__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -131394,12 +131057,6 @@ module \reg_6
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131414,7 +131071,7 @@ module \reg_6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
+    connect \A \src36__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -131429,7 +131086,7 @@ module \reg_6
     connect \Y $12
   end
   process $group_3
-    assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131438,23 +131095,17 @@ module \reg_6
         switch { \dest16__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src26__data_o \dest16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest26__data_i
+            assign \src36__data_o \dest16__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src26__data_o \reg
+            assign \src36__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -131469,7 +131120,7 @@ module \reg_6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src36__ren
+    connect \A \dmi6__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -131486,12 +131137,6 @@ module \reg_6
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131506,7 +131151,7 @@ module \reg_6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src36__ren
+    connect \A \dmi6__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -131521,101 +131166,9 @@ module \reg_6
     connect \Y $19
   end
   process $group_5
-    assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src36__data_o \dest16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src36__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src36__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi6__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi6__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -131624,14 +131177,8 @@ module \reg_6
           case 1'1
             assign \dmi6__data_o \dest16__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi6__data_o \dest26__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi6__data_o \reg
@@ -131642,7 +131189,7 @@ module \reg_6
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest16__wen }
@@ -131650,12 +131197,6 @@ module \reg_6
       case 1'1
         assign \reg$next \dest16__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest26__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest26__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -131670,34 +131211,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_7"
 module \reg_7
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src17__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src17__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src27__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src27__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src37__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src37__data_o
+  wire width 1 input 4 \src37__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi7__ren
+  wire width 64 output 5 \src37__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi7__data_o
+  wire width 1 input 6 \dmi7__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest17__wen
+  wire width 64 output 7 \dmi7__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest17__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest27__wen
+  wire width 1 input 8 \dest17__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest27__data_i
+  wire width 64 input 9 \dest17__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131726,12 +131259,6 @@ module \reg_7
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131776,12 +131303,6 @@ module \reg_7
           case 1'1
             assign \src17__data_o \dest17__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest27__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -131805,7 +131326,7 @@ module \reg_7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
+    connect \A \src37__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -131822,12 +131343,6 @@ module \reg_7
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131842,7 +131357,7 @@ module \reg_7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
+    connect \A \src37__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -131857,7 +131372,7 @@ module \reg_7
     connect \Y $12
   end
   process $group_3
-    assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131866,23 +131381,17 @@ module \reg_7
         switch { \dest17__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src27__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest27__data_i
+            assign \src37__data_o \dest17__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src27__data_o \reg
+            assign \src37__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -131897,7 +131406,7 @@ module \reg_7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src37__ren
+    connect \A \dmi7__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -131914,12 +131423,6 @@ module \reg_7
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -131934,7 +131437,7 @@ module \reg_7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src37__ren
+    connect \A \dmi7__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -131949,7 +131452,7 @@ module \reg_7
     connect \Y $19
   end
   process $group_5
-    assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -131958,108 +131461,10 @@ module \reg_7
         switch { \dest17__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src37__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src37__data_o \dest27__data_i
+            assign \dmi7__data_o \dest17__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src37__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi7__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi7__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi7__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi7__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi7__data_o \reg
@@ -132070,7 +131475,7 @@ module \reg_7
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest17__wen }
@@ -132078,12 +131483,6 @@ module \reg_7
       case 1'1
         assign \reg$next \dest17__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest27__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest27__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -132098,34 +131497,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_8"
 module \reg_8
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src18__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src18__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src28__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src28__data_o
+  wire width 1 input 4 \src38__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src38__ren
+  wire width 64 output 5 \src38__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src38__data_o
+  wire width 1 input 6 \dmi8__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi8__ren
+  wire width 64 output 7 \dmi8__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi8__data_o
+  wire width 1 input 8 \dest18__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest18__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest18__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest28__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest28__data_i
+  wire width 64 input 9 \dest18__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -132154,12 +131545,6 @@ module \reg_8
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132204,12 +131589,6 @@ module \reg_8
           case 1'1
             assign \src18__data_o \dest18__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src18__data_o \dest28__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -132233,7 +131612,7 @@ module \reg_8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src28__ren
+    connect \A \src38__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -132250,12 +131629,6 @@ module \reg_8
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132270,7 +131643,7 @@ module \reg_8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src28__ren
+    connect \A \src38__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -132285,7 +131658,7 @@ module \reg_8
     connect \Y $12
   end
   process $group_3
-    assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -132294,23 +131667,17 @@ module \reg_8
         switch { \dest18__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src28__data_o \dest18__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src28__data_o \dest28__data_i
+            assign \src38__data_o \dest18__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src28__data_o \reg
+            assign \src38__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -132325,7 +131692,7 @@ module \reg_8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src38__ren
+    connect \A \dmi8__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -132342,12 +131709,6 @@ module \reg_8
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132362,7 +131723,7 @@ module \reg_8
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src38__ren
+    connect \A \dmi8__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -132377,101 +131738,9 @@ module \reg_8
     connect \Y $19
   end
   process $group_5
-    assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src38__data_o \dest18__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src38__data_o \dest28__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src38__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi8__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi8__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi8__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -132480,14 +131749,8 @@ module \reg_8
           case 1'1
             assign \dmi8__data_o \dest18__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi8__data_o \dest28__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi8__data_o \reg
@@ -132498,7 +131761,7 @@ module \reg_8
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest18__wen }
@@ -132506,12 +131769,6 @@ module \reg_8
       case 1'1
         assign \reg$next \dest18__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest28__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest28__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -132526,34 +131783,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_9"
 module \reg_9
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src19__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src19__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src29__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src29__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src39__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src39__data_o
+  wire width 1 input 4 \src39__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi9__ren
+  wire width 64 output 5 \src39__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi9__data_o
+  wire width 1 input 6 \dmi9__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest19__wen
+  wire width 64 output 7 \dmi9__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest19__data_i
+  wire width 1 input 8 \dest19__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest29__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest29__data_i
+  wire width 64 input 9 \dest19__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -132582,12 +131831,6 @@ module \reg_9
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132632,12 +131875,6 @@ module \reg_9
           case 1'1
             assign \src19__data_o \dest19__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src19__data_o \dest29__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -132661,7 +131898,7 @@ module \reg_9
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src29__ren
+    connect \A \src39__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -132678,12 +131915,6 @@ module \reg_9
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132698,7 +131929,7 @@ module \reg_9
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src29__ren
+    connect \A \src39__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -132713,7 +131944,7 @@ module \reg_9
     connect \Y $12
   end
   process $group_3
-    assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -132722,23 +131953,17 @@ module \reg_9
         switch { \dest19__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src29__data_o \dest19__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src29__data_o \dest29__data_i
+            assign \src39__data_o \dest19__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src29__data_o \reg
+            assign \src39__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -132753,7 +131978,7 @@ module \reg_9
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src39__ren
+    connect \A \dmi9__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -132770,12 +131995,6 @@ module \reg_9
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -132790,7 +132009,7 @@ module \reg_9
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src39__ren
+    connect \A \dmi9__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -132805,101 +132024,9 @@ module \reg_9
     connect \Y $19
   end
   process $group_5
-    assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src39__data_o \dest19__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src39__data_o \dest29__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src39__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi9__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi9__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi9__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -132908,14 +132035,8 @@ module \reg_9
           case 1'1
             assign \dmi9__data_o \dest19__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi9__data_o \dest29__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi9__data_o \reg
@@ -132926,7 +132047,7 @@ module \reg_9
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest19__wen }
@@ -132934,12 +132055,6 @@ module \reg_9
       case 1'1
         assign \reg$next \dest19__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest29__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest29__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -132954,34 +132069,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_10"
 module \reg_10
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src110__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src110__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src210__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src210__data_o
+  wire width 1 input 4 \src310__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src310__ren
+  wire width 64 output 5 \src310__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src310__data_o
+  wire width 1 input 6 \dmi10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi10__ren
+  wire width 64 output 7 \dmi10__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi10__data_o
+  wire width 1 input 8 \dest110__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest110__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest110__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest210__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest210__data_i
+  wire width 64 input 9 \dest110__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -133010,12 +132117,6 @@ module \reg_10
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133060,12 +132161,6 @@ module \reg_10
           case 1'1
             assign \src110__data_o \dest110__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src110__data_o \dest210__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -133089,7 +132184,7 @@ module \reg_10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src210__ren
+    connect \A \src310__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -133106,12 +132201,6 @@ module \reg_10
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133126,7 +132215,7 @@ module \reg_10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src210__ren
+    connect \A \src310__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -133141,7 +132230,7 @@ module \reg_10
     connect \Y $12
   end
   process $group_3
-    assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -133150,23 +132239,17 @@ module \reg_10
         switch { \dest110__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src210__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src210__data_o \dest210__data_i
+            assign \src310__data_o \dest110__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src210__data_o \reg
+            assign \src310__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -133181,7 +132264,7 @@ module \reg_10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src310__ren
+    connect \A \dmi10__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -133198,12 +132281,6 @@ module \reg_10
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133218,7 +132295,7 @@ module \reg_10
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src310__ren
+    connect \A \dmi10__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -133233,7 +132310,7 @@ module \reg_10
     connect \Y $19
   end
   process $group_5
-    assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -133242,59 +132319,89 @@ module \reg_10
         switch { \dest110__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src310__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src310__data_o \dest210__data_i
+            assign \dmi10__data_o \dest110__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src310__data_o \reg
+            assign \dmi10__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest110__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest110__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
+module \reg_11
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src111__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src111__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src311__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src311__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest111__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest111__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi10__ren
+    connect \A \src111__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
+        switch { \dest111__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -133302,170 +132409,22 @@ module \reg_10
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi10__ren
+    connect \A \src111__ren
     connect \B 1'1
-    connect \Y $24
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi10__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi10__data_o \dest210__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi10__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest110__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest110__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest210__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest210__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
-module \reg_11
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src111__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src111__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src211__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src211__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src311__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src311__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi11__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi11__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest111__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest111__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest211__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest211__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src111__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src111__ren
-    connect \B 1'1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
@@ -133488,12 +132447,6 @@ module \reg_11
           case 1'1
             assign \src111__data_o \dest111__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src111__data_o \dest211__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -133517,7 +132470,7 @@ module \reg_11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src211__ren
+    connect \A \src311__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -133534,12 +132487,6 @@ module \reg_11
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133554,7 +132501,7 @@ module \reg_11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src211__ren
+    connect \A \src311__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -133569,7 +132516,7 @@ module \reg_11
     connect \Y $12
   end
   process $group_3
-    assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -133578,23 +132525,17 @@ module \reg_11
         switch { \dest111__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src211__data_o \dest111__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src211__data_o \dest211__data_i
+            assign \src311__data_o \dest111__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src211__data_o \reg
+            assign \src311__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -133609,7 +132550,7 @@ module \reg_11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src311__ren
+    connect \A \dmi11__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -133626,12 +132567,6 @@ module \reg_11
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133646,7 +132581,7 @@ module \reg_11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src311__ren
+    connect \A \dmi11__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -133661,101 +132596,9 @@ module \reg_11
     connect \Y $19
   end
   process $group_5
-    assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src311__data_o \dest111__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src311__data_o \dest211__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src311__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi11__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi11__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -133764,14 +132607,8 @@ module \reg_11
           case 1'1
             assign \dmi11__data_o \dest111__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi11__data_o \dest211__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi11__data_o \reg
@@ -133782,7 +132619,7 @@ module \reg_11
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest111__wen }
@@ -133790,12 +132627,6 @@ module \reg_11
       case 1'1
         assign \reg$next \dest111__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest211__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest211__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -133810,34 +132641,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_12"
 module \reg_12
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src112__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src112__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src212__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src212__data_o
+  wire width 1 input 4 \src312__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src312__ren
+  wire width 64 output 5 \src312__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src312__data_o
+  wire width 1 input 6 \dmi12__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi12__ren
+  wire width 64 output 7 \dmi12__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi12__data_o
+  wire width 1 input 8 \dest112__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest112__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest112__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest212__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest212__data_i
+  wire width 64 input 9 \dest112__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -133866,12 +132689,6 @@ module \reg_12
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133916,12 +132733,6 @@ module \reg_12
           case 1'1
             assign \src112__data_o \dest112__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src112__data_o \dest212__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -133945,7 +132756,7 @@ module \reg_12
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src212__ren
+    connect \A \src312__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -133962,12 +132773,6 @@ module \reg_12
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -133982,7 +132787,7 @@ module \reg_12
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src212__ren
+    connect \A \src312__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -133997,7 +132802,7 @@ module \reg_12
     connect \Y $12
   end
   process $group_3
-    assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -134006,23 +132811,17 @@ module \reg_12
         switch { \dest112__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src212__data_o \dest112__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src212__data_o \dest212__data_i
+            assign \src312__data_o \dest112__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src212__data_o \reg
+            assign \src312__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -134037,7 +132836,7 @@ module \reg_12
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src312__ren
+    connect \A \dmi12__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -134054,12 +132853,6 @@ module \reg_12
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134074,7 +132867,7 @@ module \reg_12
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src312__ren
+    connect \A \dmi12__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -134089,101 +132882,9 @@ module \reg_12
     connect \Y $19
   end
   process $group_5
-    assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src312__data_o \dest112__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src312__data_o \dest212__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src312__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi12__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi12__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -134192,14 +132893,8 @@ module \reg_12
           case 1'1
             assign \dmi12__data_o \dest112__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi12__data_o \dest212__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi12__data_o \reg
@@ -134210,7 +132905,7 @@ module \reg_12
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest112__wen }
@@ -134218,12 +132913,6 @@ module \reg_12
       case 1'1
         assign \reg$next \dest112__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest212__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest212__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -134238,34 +132927,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_13"
 module \reg_13
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src113__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src113__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src213__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src213__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src313__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src313__data_o
+  wire width 1 input 4 \src313__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi13__ren
+  wire width 64 output 5 \src313__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi13__data_o
+  wire width 1 input 6 \dmi13__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest113__wen
+  wire width 64 output 7 \dmi13__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest113__data_i
+  wire width 1 input 8 \dest113__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest213__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest213__data_i
+  wire width 64 input 9 \dest113__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -134294,12 +132975,6 @@ module \reg_13
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134344,12 +133019,6 @@ module \reg_13
           case 1'1
             assign \src113__data_o \dest113__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src113__data_o \dest213__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -134373,7 +133042,7 @@ module \reg_13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src213__ren
+    connect \A \src313__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -134390,12 +133059,6 @@ module \reg_13
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134410,7 +133073,7 @@ module \reg_13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src213__ren
+    connect \A \src313__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -134425,7 +133088,7 @@ module \reg_13
     connect \Y $12
   end
   process $group_3
-    assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -134434,23 +133097,17 @@ module \reg_13
         switch { \dest113__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src213__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src213__data_o \dest213__data_i
+            assign \src313__data_o \dest113__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src213__data_o \reg
+            assign \src313__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -134465,7 +133122,7 @@ module \reg_13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src313__ren
+    connect \A \dmi13__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -134482,12 +133139,6 @@ module \reg_13
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134502,7 +133153,7 @@ module \reg_13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src313__ren
+    connect \A \dmi13__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -134517,7 +133168,7 @@ module \reg_13
     connect \Y $19
   end
   process $group_5
-    assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -134526,207 +133177,89 @@ module \reg_13
         switch { \dest113__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src313__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src313__data_o \dest213__data_i
+            assign \dmi13__data_o \dest113__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src313__data_o \reg
+            assign \dmi13__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest113__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest113__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
+module \reg_14
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src114__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src114__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src314__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src314__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi14__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi14__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest114__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest114__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi13__ren
+    connect \A \src114__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$21 1'0
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
+        switch { \dest114__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi13__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi13__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi13__data_o \dest213__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi13__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest113__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest113__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest213__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest213__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
-module \reg_14
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src114__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src114__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src214__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src214__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src314__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src314__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi14__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi14__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest114__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest114__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest214__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest214__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src114__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -134772,12 +133305,6 @@ module \reg_14
           case 1'1
             assign \src114__data_o \dest114__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src114__data_o \dest214__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -134801,7 +133328,7 @@ module \reg_14
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src214__ren
+    connect \A \src314__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -134818,12 +133345,6 @@ module \reg_14
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134838,7 +133359,7 @@ module \reg_14
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src214__ren
+    connect \A \src314__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -134853,7 +133374,7 @@ module \reg_14
     connect \Y $12
   end
   process $group_3
-    assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -134862,23 +133383,17 @@ module \reg_14
         switch { \dest114__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src214__data_o \dest114__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src214__data_o \dest214__data_i
+            assign \src314__data_o \dest114__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src214__data_o \reg
+            assign \src314__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -134893,7 +133408,7 @@ module \reg_14
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src314__ren
+    connect \A \dmi14__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -134910,12 +133425,6 @@ module \reg_14
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -134930,7 +133439,7 @@ module \reg_14
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src314__ren
+    connect \A \dmi14__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -134945,101 +133454,9 @@ module \reg_14
     connect \Y $19
   end
   process $group_5
-    assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src314__data_o \dest114__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src314__data_o \dest214__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src314__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi14__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi14__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -135048,14 +133465,8 @@ module \reg_14
           case 1'1
             assign \dmi14__data_o \dest114__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi14__data_o \dest214__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi14__data_o \reg
@@ -135066,7 +133477,7 @@ module \reg_14
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest114__wen }
@@ -135074,12 +133485,6 @@ module \reg_14
       case 1'1
         assign \reg$next \dest114__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest214__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest214__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -135094,34 +133499,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_15"
 module \reg_15
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src115__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src115__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src215__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src215__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src315__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src315__data_o
+  wire width 1 input 4 \src315__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi15__ren
+  wire width 64 output 5 \src315__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi15__data_o
+  wire width 1 input 6 \dmi15__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest115__wen
+  wire width 64 output 7 \dmi15__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest115__data_i
+  wire width 1 input 8 \dest115__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest215__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest215__data_i
+  wire width 64 input 9 \dest115__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -135150,12 +133547,6 @@ module \reg_15
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135200,12 +133591,6 @@ module \reg_15
           case 1'1
             assign \src115__data_o \dest115__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src115__data_o \dest215__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -135229,7 +133614,7 @@ module \reg_15
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src215__ren
+    connect \A \src315__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -135246,12 +133631,6 @@ module \reg_15
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135266,7 +133645,7 @@ module \reg_15
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src215__ren
+    connect \A \src315__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -135281,7 +133660,7 @@ module \reg_15
     connect \Y $12
   end
   process $group_3
-    assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -135290,23 +133669,17 @@ module \reg_15
         switch { \dest115__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src215__data_o \dest115__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src215__data_o \dest215__data_i
+            assign \src315__data_o \dest115__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src215__data_o \reg
+            assign \src315__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -135321,7 +133694,7 @@ module \reg_15
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src315__ren
+    connect \A \dmi15__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -135338,12 +133711,6 @@ module \reg_15
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135358,7 +133725,7 @@ module \reg_15
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src315__ren
+    connect \A \dmi15__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -135373,101 +133740,9 @@ module \reg_15
     connect \Y $19
   end
   process $group_5
-    assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src315__data_o \dest115__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src315__data_o \dest215__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src315__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi15__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi15__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -135476,14 +133751,8 @@ module \reg_15
           case 1'1
             assign \dmi15__data_o \dest115__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi15__data_o \dest215__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi15__data_o \reg
@@ -135494,7 +133763,7 @@ module \reg_15
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest115__wen }
@@ -135502,12 +133771,6 @@ module \reg_15
       case 1'1
         assign \reg$next \dest115__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest215__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest215__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -135522,34 +133785,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_16"
 module \reg_16
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src116__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src116__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src216__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src216__data_o
+  wire width 1 input 4 \src316__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src316__ren
+  wire width 64 output 5 \src316__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src316__data_o
+  wire width 1 input 6 \dmi16__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi16__ren
+  wire width 64 output 7 \dmi16__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi16__data_o
+  wire width 1 input 8 \dest116__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest116__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest116__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest216__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest216__data_i
+  wire width 64 input 9 \dest116__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -135578,12 +133833,6 @@ module \reg_16
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135628,12 +133877,6 @@ module \reg_16
           case 1'1
             assign \src116__data_o \dest116__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src116__data_o \dest216__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -135657,7 +133900,7 @@ module \reg_16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src216__ren
+    connect \A \src316__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -135674,12 +133917,6 @@ module \reg_16
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135694,7 +133931,7 @@ module \reg_16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src216__ren
+    connect \A \src316__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -135709,7 +133946,7 @@ module \reg_16
     connect \Y $12
   end
   process $group_3
-    assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -135718,23 +133955,17 @@ module \reg_16
         switch { \dest116__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src216__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src216__data_o \dest216__data_i
+            assign \src316__data_o \dest116__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src216__data_o \reg
+            assign \src316__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -135749,7 +133980,7 @@ module \reg_16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src316__ren
+    connect \A \dmi16__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -135766,12 +133997,6 @@ module \reg_16
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -135786,7 +134011,7 @@ module \reg_16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src316__ren
+    connect \A \dmi16__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -135801,7 +134026,7 @@ module \reg_16
     connect \Y $19
   end
   process $group_5
-    assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -135810,208 +134035,90 @@ module \reg_16
         switch { \dest116__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src316__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src316__data_o \dest216__data_i
+            assign \dmi16__data_o \dest116__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src316__data_o \reg
+            assign \dmi16__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest116__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest116__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
+module \reg_17
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src117__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src117__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src317__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src317__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi17__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi17__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest117__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest117__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi16__ren
+    connect \A \src117__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi16__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi16__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi16__data_o \dest216__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi16__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest116__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest116__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest216__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest216__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
-module \reg_17
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src117__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src117__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src217__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src217__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src317__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src317__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi17__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi17__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest117__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest117__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest217__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest217__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src117__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \dest117__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136056,12 +134163,6 @@ module \reg_17
           case 1'1
             assign \src117__data_o \dest117__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src117__data_o \dest217__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -136085,7 +134186,7 @@ module \reg_17
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src217__ren
+    connect \A \src317__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -136102,12 +134203,6 @@ module \reg_17
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136122,7 +134217,7 @@ module \reg_17
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src217__ren
+    connect \A \src317__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -136137,7 +134232,7 @@ module \reg_17
     connect \Y $12
   end
   process $group_3
-    assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -136146,23 +134241,17 @@ module \reg_17
         switch { \dest117__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src217__data_o \dest117__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src217__data_o \dest217__data_i
+            assign \src317__data_o \dest117__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src217__data_o \reg
+            assign \src317__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -136177,7 +134266,7 @@ module \reg_17
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src317__ren
+    connect \A \dmi17__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -136194,12 +134283,6 @@ module \reg_17
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136214,7 +134297,7 @@ module \reg_17
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src317__ren
+    connect \A \dmi17__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -136229,101 +134312,9 @@ module \reg_17
     connect \Y $19
   end
   process $group_5
-    assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src317__data_o \dest117__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src317__data_o \dest217__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src317__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi17__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi17__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -136332,14 +134323,8 @@ module \reg_17
           case 1'1
             assign \dmi17__data_o \dest117__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi17__data_o \dest217__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi17__data_o \reg
@@ -136350,7 +134335,7 @@ module \reg_17
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest117__wen }
@@ -136358,12 +134343,6 @@ module \reg_17
       case 1'1
         assign \reg$next \dest117__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest217__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest217__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -136378,34 +134357,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_18"
 module \reg_18
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src118__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src118__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src218__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src218__data_o
+  wire width 1 input 4 \src318__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src318__ren
+  wire width 64 output 5 \src318__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src318__data_o
+  wire width 1 input 6 \dmi18__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi18__ren
+  wire width 64 output 7 \dmi18__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi18__data_o
+  wire width 1 input 8 \dest118__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest118__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest118__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest218__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest218__data_i
+  wire width 64 input 9 \dest118__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -136434,12 +134405,6 @@ module \reg_18
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136484,12 +134449,6 @@ module \reg_18
           case 1'1
             assign \src118__data_o \dest118__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src118__data_o \dest218__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -136513,7 +134472,7 @@ module \reg_18
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src218__ren
+    connect \A \src318__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -136530,12 +134489,6 @@ module \reg_18
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136550,7 +134503,7 @@ module \reg_18
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src218__ren
+    connect \A \src318__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -136565,7 +134518,7 @@ module \reg_18
     connect \Y $12
   end
   process $group_3
-    assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -136574,23 +134527,17 @@ module \reg_18
         switch { \dest118__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src218__data_o \dest118__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src218__data_o \dest218__data_i
+            assign \src318__data_o \dest118__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src218__data_o \reg
+            assign \src318__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -136605,7 +134552,7 @@ module \reg_18
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src318__ren
+    connect \A \dmi18__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -136622,12 +134569,6 @@ module \reg_18
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136642,7 +134583,7 @@ module \reg_18
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src318__ren
+    connect \A \dmi18__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -136657,101 +134598,9 @@ module \reg_18
     connect \Y $19
   end
   process $group_5
-    assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src318__data_o \dest118__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src318__data_o \dest218__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src318__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi18__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi18__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -136760,14 +134609,8 @@ module \reg_18
           case 1'1
             assign \dmi18__data_o \dest118__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi18__data_o \dest218__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi18__data_o \reg
@@ -136778,7 +134621,7 @@ module \reg_18
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest118__wen }
@@ -136786,12 +134629,6 @@ module \reg_18
       case 1'1
         assign \reg$next \dest118__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest218__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest218__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -136806,34 +134643,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_19"
 module \reg_19
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src119__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src119__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src219__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src219__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src319__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src319__data_o
+  wire width 1 input 4 \src319__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi19__ren
+  wire width 64 output 5 \src319__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi19__data_o
+  wire width 1 input 6 \dmi19__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest119__wen
+  wire width 64 output 7 \dmi19__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest119__data_i
+  wire width 1 input 8 \dest119__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest219__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest219__data_i
+  wire width 64 input 9 \dest119__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -136862,12 +134691,6 @@ module \reg_19
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136912,12 +134735,6 @@ module \reg_19
           case 1'1
             assign \src119__data_o \dest119__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src119__data_o \dest219__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -136941,7 +134758,7 @@ module \reg_19
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src219__ren
+    connect \A \src319__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -136958,12 +134775,6 @@ module \reg_19
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -136978,7 +134789,7 @@ module \reg_19
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src219__ren
+    connect \A \src319__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -136993,7 +134804,7 @@ module \reg_19
     connect \Y $12
   end
   process $group_3
-    assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -137002,23 +134813,17 @@ module \reg_19
         switch { \dest119__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src219__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src219__data_o \dest219__data_i
+            assign \src319__data_o \dest119__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src219__data_o \reg
+            assign \src319__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -137033,7 +134838,7 @@ module \reg_19
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src319__ren
+    connect \A \dmi19__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -137050,12 +134855,6 @@ module \reg_19
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137070,7 +134869,7 @@ module \reg_19
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src319__ren
+    connect \A \dmi19__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -137085,7 +134884,7 @@ module \reg_19
     connect \Y $19
   end
   process $group_5
-    assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -137094,193 +134893,81 @@ module \reg_19
         switch { \dest119__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src319__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src319__data_o \dest219__data_i
+            assign \dmi19__data_o \dest119__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src319__data_o \reg
+            assign \dmi19__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest119__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest119__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
+module \reg_20
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src120__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src120__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src320__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src320__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi20__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi20__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest120__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest120__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi19__ren
+    connect \A \src120__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi19__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi19__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi19__data_o \dest219__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi19__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest119__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest119__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest219__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest219__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
-module \reg_20
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src120__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src120__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src220__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src220__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src320__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src320__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi20__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi20__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest120__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest120__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest220__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest220__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src120__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         assign \wr_detect 1'0
@@ -137290,12 +134977,6 @@ module \reg_20
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137340,12 +135021,6 @@ module \reg_20
           case 1'1
             assign \src120__data_o \dest120__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src120__data_o \dest220__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -137369,7 +135044,7 @@ module \reg_20
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src220__ren
+    connect \A \src320__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -137386,12 +135061,6 @@ module \reg_20
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137406,7 +135075,7 @@ module \reg_20
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src220__ren
+    connect \A \src320__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -137421,7 +135090,7 @@ module \reg_20
     connect \Y $12
   end
   process $group_3
-    assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -137430,23 +135099,17 @@ module \reg_20
         switch { \dest120__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src220__data_o \dest120__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src220__data_o \dest220__data_i
+            assign \src320__data_o \dest120__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src220__data_o \reg
+            assign \src320__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -137461,7 +135124,7 @@ module \reg_20
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src320__ren
+    connect \A \dmi20__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -137478,12 +135141,6 @@ module \reg_20
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137498,7 +135155,7 @@ module \reg_20
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src320__ren
+    connect \A \dmi20__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -137513,101 +135170,9 @@ module \reg_20
     connect \Y $19
   end
   process $group_5
-    assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src320__data_o \dest120__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src320__data_o \dest220__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src320__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi20__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi20__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -137616,14 +135181,8 @@ module \reg_20
           case 1'1
             assign \dmi20__data_o \dest120__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi20__data_o \dest220__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi20__data_o \reg
@@ -137634,7 +135193,7 @@ module \reg_20
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest120__wen }
@@ -137642,12 +135201,6 @@ module \reg_20
       case 1'1
         assign \reg$next \dest120__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest220__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest220__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -137662,34 +135215,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_21"
 module \reg_21
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src121__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src121__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src221__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src221__data_o
+  wire width 1 input 4 \src321__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src321__ren
+  wire width 64 output 5 \src321__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src321__data_o
+  wire width 1 input 6 \dmi21__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi21__ren
+  wire width 64 output 7 \dmi21__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi21__data_o
+  wire width 1 input 8 \dest121__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest121__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest121__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest221__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest221__data_i
+  wire width 64 input 9 \dest121__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -137718,12 +135263,6 @@ module \reg_21
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137768,12 +135307,6 @@ module \reg_21
           case 1'1
             assign \src121__data_o \dest121__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src121__data_o \dest221__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -137797,7 +135330,7 @@ module \reg_21
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src221__ren
+    connect \A \src321__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -137814,12 +135347,6 @@ module \reg_21
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137834,7 +135361,7 @@ module \reg_21
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src221__ren
+    connect \A \src321__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -137849,7 +135376,7 @@ module \reg_21
     connect \Y $12
   end
   process $group_3
-    assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -137858,23 +135385,17 @@ module \reg_21
         switch { \dest121__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src221__data_o \dest121__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src221__data_o \dest221__data_i
+            assign \src321__data_o \dest121__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src221__data_o \reg
+            assign \src321__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -137889,7 +135410,7 @@ module \reg_21
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src321__ren
+    connect \A \dmi21__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -137906,12 +135427,6 @@ module \reg_21
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -137926,7 +135441,7 @@ module \reg_21
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src321__ren
+    connect \A \dmi21__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -137941,101 +135456,9 @@ module \reg_21
     connect \Y $19
   end
   process $group_5
-    assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src321__data_o \dest121__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src321__data_o \dest221__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src321__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi21__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi21__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -138044,14 +135467,8 @@ module \reg_21
           case 1'1
             assign \dmi21__data_o \dest121__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi21__data_o \dest221__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi21__data_o \reg
@@ -138062,7 +135479,7 @@ module \reg_21
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest121__wen }
@@ -138070,12 +135487,6 @@ module \reg_21
       case 1'1
         assign \reg$next \dest121__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest221__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest221__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -138090,34 +135501,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_22"
 module \reg_22
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src122__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src122__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src222__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src222__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src322__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src322__data_o
+  wire width 1 input 4 \src322__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi22__ren
+  wire width 64 output 5 \src322__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi22__data_o
+  wire width 1 input 6 \dmi22__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest122__wen
+  wire width 64 output 7 \dmi22__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest122__data_i
+  wire width 1 input 8 \dest122__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest222__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest222__data_i
+  wire width 64 input 9 \dest122__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -138146,12 +135549,6 @@ module \reg_22
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138196,12 +135593,6 @@ module \reg_22
           case 1'1
             assign \src122__data_o \dest122__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src122__data_o \dest222__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -138225,7 +135616,7 @@ module \reg_22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src222__ren
+    connect \A \src322__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -138242,12 +135633,6 @@ module \reg_22
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138262,7 +135647,7 @@ module \reg_22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src222__ren
+    connect \A \src322__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -138277,7 +135662,7 @@ module \reg_22
     connect \Y $12
   end
   process $group_3
-    assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -138286,23 +135671,17 @@ module \reg_22
         switch { \dest122__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src222__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src222__data_o \dest222__data_i
+            assign \src322__data_o \dest122__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src222__data_o \reg
+            assign \src322__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -138317,7 +135696,7 @@ module \reg_22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src322__ren
+    connect \A \dmi22__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -138334,12 +135713,6 @@ module \reg_22
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138354,7 +135727,7 @@ module \reg_22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src322__ren
+    connect \A \dmi22__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -138369,7 +135742,7 @@ module \reg_22
     connect \Y $19
   end
   process $group_5
-    assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -138378,193 +135751,81 @@ module \reg_22
         switch { \dest122__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src322__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src322__data_o \dest222__data_i
+            assign \dmi22__data_o \dest122__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src322__data_o \reg
+            assign \dmi22__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest122__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest122__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
+module \reg_23
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src123__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src123__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src323__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src323__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi23__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi23__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest123__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest123__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi22__ren
+    connect \A \src123__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi22__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi22__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi22__data_o \dest222__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi22__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest122__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest122__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest222__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest222__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
-module \reg_23
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src123__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src123__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src223__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src223__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src323__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src323__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest123__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest123__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest223__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest223__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src123__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         assign \wr_detect 1'0
@@ -138574,12 +135835,6 @@ module \reg_23
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138624,12 +135879,6 @@ module \reg_23
           case 1'1
             assign \src123__data_o \dest123__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src123__data_o \dest223__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -138653,7 +135902,7 @@ module \reg_23
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src223__ren
+    connect \A \src323__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -138670,12 +135919,6 @@ module \reg_23
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138690,7 +135933,7 @@ module \reg_23
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src223__ren
+    connect \A \src323__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -138705,7 +135948,7 @@ module \reg_23
     connect \Y $12
   end
   process $group_3
-    assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -138714,23 +135957,17 @@ module \reg_23
         switch { \dest123__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src223__data_o \dest123__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src223__data_o \dest223__data_i
+            assign \src323__data_o \dest123__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src223__data_o \reg
+            assign \src323__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -138745,7 +135982,7 @@ module \reg_23
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src323__ren
+    connect \A \dmi23__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -138762,12 +135999,6 @@ module \reg_23
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -138782,7 +136013,7 @@ module \reg_23
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src323__ren
+    connect \A \dmi23__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -138797,101 +136028,9 @@ module \reg_23
     connect \Y $19
   end
   process $group_5
-    assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src323__data_o \dest123__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src323__data_o \dest223__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src323__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi23__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi23__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -138900,14 +136039,8 @@ module \reg_23
           case 1'1
             assign \dmi23__data_o \dest123__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi23__data_o \dest223__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi23__data_o \reg
@@ -138918,7 +136051,7 @@ module \reg_23
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest123__wen }
@@ -138926,12 +136059,6 @@ module \reg_23
       case 1'1
         assign \reg$next \dest123__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest223__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest223__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -138946,34 +136073,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_24"
 module \reg_24
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src124__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src124__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src224__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src224__data_o
+  wire width 1 input 4 \src324__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src324__ren
+  wire width 64 output 5 \src324__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src324__data_o
+  wire width 1 input 6 \dmi24__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi24__ren
+  wire width 64 output 7 \dmi24__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi24__data_o
+  wire width 1 input 8 \dest124__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest124__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest124__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest224__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest224__data_i
+  wire width 64 input 9 \dest124__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139002,12 +136121,6 @@ module \reg_24
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139052,12 +136165,6 @@ module \reg_24
           case 1'1
             assign \src124__data_o \dest124__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src124__data_o \dest224__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -139081,7 +136188,7 @@ module \reg_24
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src224__ren
+    connect \A \src324__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -139098,12 +136205,6 @@ module \reg_24
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139118,7 +136219,7 @@ module \reg_24
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src224__ren
+    connect \A \src324__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -139133,7 +136234,7 @@ module \reg_24
     connect \Y $12
   end
   process $group_3
-    assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139142,23 +136243,17 @@ module \reg_24
         switch { \dest124__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src224__data_o \dest124__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src224__data_o \dest224__data_i
+            assign \src324__data_o \dest124__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src224__data_o \reg
+            assign \src324__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -139173,7 +136268,7 @@ module \reg_24
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src324__ren
+    connect \A \dmi24__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -139190,12 +136285,6 @@ module \reg_24
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139210,7 +136299,7 @@ module \reg_24
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src324__ren
+    connect \A \dmi24__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -139225,101 +136314,9 @@ module \reg_24
     connect \Y $19
   end
   process $group_5
-    assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src324__data_o \dest124__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src324__data_o \dest224__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src324__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi24__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi24__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -139328,14 +136325,8 @@ module \reg_24
           case 1'1
             assign \dmi24__data_o \dest124__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi24__data_o \dest224__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi24__data_o \reg
@@ -139346,7 +136337,7 @@ module \reg_24
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest124__wen }
@@ -139354,12 +136345,6 @@ module \reg_24
       case 1'1
         assign \reg$next \dest124__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest224__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest224__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -139374,34 +136359,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_25"
 module \reg_25
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src125__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src125__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src225__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src225__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src325__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src325__data_o
+  wire width 1 input 4 \src325__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi25__ren
+  wire width 64 output 5 \src325__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi25__data_o
+  wire width 1 input 6 \dmi25__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest125__wen
+  wire width 64 output 7 \dmi25__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest125__data_i
+  wire width 1 input 8 \dest125__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest225__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest225__data_i
+  wire width 64 input 9 \dest125__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139430,12 +136407,6 @@ module \reg_25
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139480,12 +136451,6 @@ module \reg_25
           case 1'1
             assign \src125__data_o \dest125__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src125__data_o \dest225__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -139509,7 +136474,7 @@ module \reg_25
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src225__ren
+    connect \A \src325__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -139526,12 +136491,6 @@ module \reg_25
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139546,7 +136505,7 @@ module \reg_25
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src225__ren
+    connect \A \src325__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -139561,7 +136520,7 @@ module \reg_25
     connect \Y $12
   end
   process $group_3
-    assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139570,23 +136529,17 @@ module \reg_25
         switch { \dest125__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src225__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src225__data_o \dest225__data_i
+            assign \src325__data_o \dest125__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src225__data_o \reg
+            assign \src325__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -139601,7 +136554,7 @@ module \reg_25
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src325__ren
+    connect \A \dmi25__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -139618,12 +136571,6 @@ module \reg_25
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139638,7 +136585,7 @@ module \reg_25
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src325__ren
+    connect \A \dmi25__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -139653,7 +136600,7 @@ module \reg_25
     connect \Y $19
   end
   process $group_5
-    assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139662,193 +136609,81 @@ module \reg_25
         switch { \dest125__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src325__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src325__data_o \dest225__data_i
+            assign \dmi25__data_o \dest125__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src325__data_o \reg
+            assign \dmi25__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest125__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest125__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
+module \reg_26
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src126__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src126__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src326__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src326__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi26__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi26__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest126__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest126__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi25__ren
+    connect \A \src126__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi25__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi25__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi25__data_o \dest225__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi25__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest125__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest125__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest225__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest225__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
-module \reg_26
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src126__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src126__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src226__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src226__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src326__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src326__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest126__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest126__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest226__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest226__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src126__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         assign \wr_detect 1'0
@@ -139858,12 +136693,6 @@ module \reg_26
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139908,12 +136737,6 @@ module \reg_26
           case 1'1
             assign \src126__data_o \dest126__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src126__data_o \dest226__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -139937,7 +136760,7 @@ module \reg_26
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src226__ren
+    connect \A \src326__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -139954,12 +136777,6 @@ module \reg_26
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -139974,7 +136791,7 @@ module \reg_26
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src226__ren
+    connect \A \src326__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -139989,7 +136806,7 @@ module \reg_26
     connect \Y $12
   end
   process $group_3
-    assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -139998,23 +136815,17 @@ module \reg_26
         switch { \dest126__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src226__data_o \dest126__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src226__data_o \dest226__data_i
+            assign \src326__data_o \dest126__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src226__data_o \reg
+            assign \src326__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -140029,7 +136840,7 @@ module \reg_26
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src326__ren
+    connect \A \dmi26__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -140046,12 +136857,6 @@ module \reg_26
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140066,7 +136871,7 @@ module \reg_26
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src326__ren
+    connect \A \dmi26__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -140081,101 +136886,9 @@ module \reg_26
     connect \Y $19
   end
   process $group_5
-    assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src326__data_o \dest126__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src326__data_o \dest226__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src326__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi26__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi26__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -140184,14 +136897,8 @@ module \reg_26
           case 1'1
             assign \dmi26__data_o \dest126__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi26__data_o \dest226__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi26__data_o \reg
@@ -140202,7 +136909,7 @@ module \reg_26
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest126__wen }
@@ -140210,12 +136917,6 @@ module \reg_26
       case 1'1
         assign \reg$next \dest126__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest226__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest226__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -140230,34 +136931,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_27"
 module \reg_27
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src127__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src127__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src227__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src227__data_o
+  wire width 1 input 4 \src327__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src327__ren
+  wire width 64 output 5 \src327__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src327__data_o
+  wire width 1 input 6 \dmi27__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi27__ren
+  wire width 64 output 7 \dmi27__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi27__data_o
+  wire width 1 input 8 \dest127__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest127__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest127__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest227__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest227__data_i
+  wire width 64 input 9 \dest127__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -140286,12 +136979,6 @@ module \reg_27
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140336,12 +137023,6 @@ module \reg_27
           case 1'1
             assign \src127__data_o \dest127__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src127__data_o \dest227__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -140365,7 +137046,7 @@ module \reg_27
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src227__ren
+    connect \A \src327__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -140382,12 +137063,6 @@ module \reg_27
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140402,7 +137077,7 @@ module \reg_27
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src227__ren
+    connect \A \src327__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -140417,7 +137092,7 @@ module \reg_27
     connect \Y $12
   end
   process $group_3
-    assign \src227__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -140426,23 +137101,17 @@ module \reg_27
         switch { \dest127__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src227__data_o \dest127__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src227__data_o \dest227__data_i
+            assign \src327__data_o \dest127__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src227__data_o \reg
+            assign \src327__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src227__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -140457,7 +137126,7 @@ module \reg_27
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src327__ren
+    connect \A \dmi27__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -140474,12 +137143,6 @@ module \reg_27
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140494,7 +137157,7 @@ module \reg_27
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src327__ren
+    connect \A \dmi27__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -140509,101 +137172,9 @@ module \reg_27
     connect \Y $19
   end
   process $group_5
-    assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest127__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src327__data_o \dest127__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src327__data_o \dest227__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src327__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi27__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest127__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi27__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -140612,14 +137183,8 @@ module \reg_27
           case 1'1
             assign \dmi27__data_o \dest127__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest227__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi27__data_o \dest227__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi27__data_o \reg
@@ -140630,7 +137195,7 @@ module \reg_27
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest127__wen }
@@ -140638,12 +137203,6 @@ module \reg_27
       case 1'1
         assign \reg$next \dest127__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest227__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest227__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -140658,34 +137217,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_28"
 module \reg_28
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src128__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src128__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src228__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src228__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src328__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src328__data_o
+  wire width 1 input 4 \src328__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi28__ren
+  wire width 64 output 5 \src328__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi28__data_o
+  wire width 1 input 6 \dmi28__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest128__wen
+  wire width 64 output 7 \dmi28__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest128__data_i
+  wire width 1 input 8 \dest128__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest228__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest228__data_i
+  wire width 64 input 9 \dest128__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -140714,12 +137265,6 @@ module \reg_28
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140764,12 +137309,6 @@ module \reg_28
           case 1'1
             assign \src128__data_o \dest128__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src128__data_o \dest228__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -140793,7 +137332,7 @@ module \reg_28
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src228__ren
+    connect \A \src328__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -140810,12 +137349,6 @@ module \reg_28
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140830,7 +137363,7 @@ module \reg_28
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src228__ren
+    connect \A \src328__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -140845,7 +137378,7 @@ module \reg_28
     connect \Y $12
   end
   process $group_3
-    assign \src228__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -140854,23 +137387,17 @@ module \reg_28
         switch { \dest128__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src228__data_o \dest128__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src228__data_o \dest228__data_i
+            assign \src328__data_o \dest128__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src228__data_o \reg
+            assign \src328__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src228__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -140885,7 +137412,7 @@ module \reg_28
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src328__ren
+    connect \A \dmi28__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -140902,12 +137429,6 @@ module \reg_28
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -140922,7 +137443,7 @@ module \reg_28
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src328__ren
+    connect \A \dmi28__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -140937,7 +137458,7 @@ module \reg_28
     connect \Y $19
   end
   process $group_5
-    assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -140946,193 +137467,81 @@ module \reg_28
         switch { \dest128__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src328__data_o \dest128__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src328__data_o \dest228__data_i
+            assign \dmi28__data_o \dest128__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src328__data_o \reg
+            assign \dmi28__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_6
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest128__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest128__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_29"
+module \reg_29
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src129__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src129__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src329__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src329__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \dmi29__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \dmi29__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dest129__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \dest129__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \dmi28__ren
+    connect \A \src129__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest128__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi28__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest128__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi28__data_o \dest128__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest228__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi28__data_o \dest228__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi28__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest128__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest128__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest228__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest228__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_29"
-module \reg_29
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src129__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src129__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src229__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src229__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src329__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src329__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi29__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi29__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest129__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest129__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest229__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest229__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src129__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         assign \wr_detect 1'0
@@ -141142,12 +137551,6 @@ module \reg_29
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141192,12 +137595,6 @@ module \reg_29
           case 1'1
             assign \src129__data_o \dest129__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src129__data_o \dest229__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -141221,7 +137618,7 @@ module \reg_29
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src229__ren
+    connect \A \src329__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -141238,12 +137635,6 @@ module \reg_29
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141258,7 +137649,7 @@ module \reg_29
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src229__ren
+    connect \A \src329__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -141273,7 +137664,7 @@ module \reg_29
     connect \Y $12
   end
   process $group_3
-    assign \src229__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -141282,23 +137673,17 @@ module \reg_29
         switch { \dest129__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src229__data_o \dest129__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src229__data_o \dest229__data_i
+            assign \src329__data_o \dest129__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src229__data_o \reg
+            assign \src329__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src229__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -141313,7 +137698,7 @@ module \reg_29
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src329__ren
+    connect \A \dmi29__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -141330,12 +137715,6 @@ module \reg_29
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141350,7 +137729,7 @@ module \reg_29
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src329__ren
+    connect \A \dmi29__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -141365,101 +137744,9 @@ module \reg_29
     connect \Y $19
   end
   process $group_5
-    assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest129__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src329__data_o \dest129__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src329__data_o \dest229__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src329__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi29__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest129__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi29__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -141468,14 +137755,8 @@ module \reg_29
           case 1'1
             assign \dmi29__data_o \dest129__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest229__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi29__data_o \dest229__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi29__data_o \reg
@@ -141486,7 +137767,7 @@ module \reg_29
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest129__wen }
@@ -141494,12 +137775,6 @@ module \reg_29
       case 1'1
         assign \reg$next \dest129__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest229__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest229__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -141514,34 +137789,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_30"
 module \reg_30
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src130__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src130__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src230__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src230__data_o
+  wire width 1 input 4 \src330__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src330__ren
+  wire width 64 output 5 \src330__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src330__data_o
+  wire width 1 input 6 \dmi30__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi30__ren
+  wire width 64 output 7 \dmi30__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi30__data_o
+  wire width 1 input 8 \dest130__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest130__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest130__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest230__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest230__data_i
+  wire width 64 input 9 \dest130__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -141570,12 +137837,6 @@ module \reg_30
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141620,12 +137881,6 @@ module \reg_30
           case 1'1
             assign \src130__data_o \dest130__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src130__data_o \dest230__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -141649,7 +137904,7 @@ module \reg_30
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src230__ren
+    connect \A \src330__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -141666,12 +137921,6 @@ module \reg_30
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141686,7 +137935,7 @@ module \reg_30
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src230__ren
+    connect \A \src330__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -141701,7 +137950,7 @@ module \reg_30
     connect \Y $12
   end
   process $group_3
-    assign \src230__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -141710,23 +137959,17 @@ module \reg_30
         switch { \dest130__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src230__data_o \dest130__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src230__data_o \dest230__data_i
+            assign \src330__data_o \dest130__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src230__data_o \reg
+            assign \src330__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src230__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -141741,7 +137984,7 @@ module \reg_30
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src330__ren
+    connect \A \dmi30__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -141758,12 +138001,6 @@ module \reg_30
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -141778,7 +138015,7 @@ module \reg_30
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src330__ren
+    connect \A \dmi30__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -141793,101 +138030,9 @@ module \reg_30
     connect \Y $19
   end
   process $group_5
-    assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest130__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src330__data_o \dest130__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src330__data_o \dest230__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src330__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi30__ren
-    connect \B 1'1
-    connect \Y $22
-  end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest130__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi30__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
     assign \dmi30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
@@ -141896,14 +138041,8 @@ module \reg_30
           case 1'1
             assign \dmi30__data_o \dest130__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest230__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi30__data_o \dest230__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
             assign \dmi30__data_o \reg
@@ -141914,7 +138053,7 @@ module \reg_30
     end
     sync init
   end
-  process $group_8
+  process $group_6
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest130__wen }
@@ -141922,12 +138061,6 @@ module \reg_30
       case 1'1
         assign \reg$next \dest130__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest230__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest230__data_i
-    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
       case 1'1
@@ -141942,34 +138075,26 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_31"
 module \reg_31
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src131__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 3 \src131__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src231__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src231__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src331__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src331__data_o
+  wire width 1 input 4 \src331__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dmi31__ren
+  wire width 64 output 5 \src331__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \dmi31__data_o
+  wire width 1 input 6 \dmi31__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest131__wen
+  wire width 64 output 7 \dmi31__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest131__data_i
+  wire width 1 input 8 \dest131__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest231__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest231__data_i
+  wire width 64 input 9 \dest131__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -141998,12 +138123,6 @@ module \reg_31
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -142048,12 +138167,6 @@ module \reg_31
           case 1'1
             assign \src131__data_o \dest131__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src131__data_o \dest231__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
@@ -142077,7 +138190,7 @@ module \reg_31
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src231__ren
+    connect \A \src331__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -142094,12 +138207,6 @@ module \reg_31
           case 1'1
             assign \wr_detect$7 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -142114,7 +138221,7 @@ module \reg_31
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src231__ren
+    connect \A \src331__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -142129,7 +138236,7 @@ module \reg_31
     connect \Y $12
   end
   process $group_3
-    assign \src231__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -142138,23 +138245,17 @@ module \reg_31
         switch { \dest131__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src231__data_o \dest131__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src231__data_o \dest231__data_i
+            assign \src331__data_o \dest131__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src231__data_o \reg
+            assign \src331__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src231__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -142169,7 +138270,7 @@ module \reg_31
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src331__ren
+    connect \A \dmi31__ren
     connect \B 1'1
     connect \Y $15
   end
@@ -142186,12 +138287,6 @@ module \reg_31
           case 1'1
             assign \wr_detect$14 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -142206,7 +138301,7 @@ module \reg_31
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src331__ren
+    connect \A \dmi31__ren
     connect \B 1'1
     connect \Y $17
   end
@@ -142221,7 +138316,7 @@ module \reg_31
     connect \Y $19
   end
   process $group_5
-    assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $17 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -142230,147 +138325,43 @@ module \reg_31
         switch { \dest131__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src331__data_o \dest131__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src331__data_o \dest231__data_i
+            assign \dmi31__data_o \dest131__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $19 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src331__data_o \reg
+            assign \dmi31__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi31__ren
-    connect \B 1'1
-    connect \Y $22
-  end
   process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest131__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
       case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest131__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \reg$next \dest131__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dmi31__ren
-    connect \B 1'1
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest131__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi31__data_o \dest131__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest231__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \dmi31__data_o \dest231__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \dmi31__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest131__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest131__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest231__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest231__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int"
 module \int
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 32 input 1 \dmi__ren
@@ -142381,32 +138372,20 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 4 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 5 \src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 6 \src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 7 \src3__ren
+  wire width 32 input 5 \src3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 8 \src3__data_o
+  wire width 64 output 6 \src3__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 9 \wen
+  wire width 32 input 7 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 10 \data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 11 \wen$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 12 \data_i$2
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 13 \coresync_rst
+  wire width 64 input 8 \data_i
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 9 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_src10__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_src20__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_src20__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src30__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_src30__data_o
@@ -142418,35 +138397,23 @@ module \int
   wire width 1 \reg_0_dest10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_dest10__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_dest20__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_dest20__data_i
   cell \reg_0 \reg_0
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src10__ren \reg_0_src10__ren
     connect \src10__data_o \reg_0_src10__data_o
-    connect \src20__ren \reg_0_src20__ren
-    connect \src20__data_o \reg_0_src20__data_o
     connect \src30__ren \reg_0_src30__ren
     connect \src30__data_o \reg_0_src30__data_o
     connect \dmi0__ren \reg_0_dmi0__ren
     connect \dmi0__data_o \reg_0_dmi0__data_o
     connect \dest10__wen \reg_0_dest10__wen
     connect \dest10__data_i \reg_0_dest10__data_i
-    connect \dest20__wen \reg_0_dest20__wen
-    connect \dest20__data_i \reg_0_dest20__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_1_src11__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_src11__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_src21__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_src21__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_1_src31__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_src31__data_o
@@ -142458,35 +138425,23 @@ module \int
   wire width 1 \reg_1_dest11__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_dest11__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_dest21__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_dest21__data_i
   cell \reg_1 \reg_1
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src11__ren \reg_1_src11__ren
     connect \src11__data_o \reg_1_src11__data_o
-    connect \src21__ren \reg_1_src21__ren
-    connect \src21__data_o \reg_1_src21__data_o
     connect \src31__ren \reg_1_src31__ren
     connect \src31__data_o \reg_1_src31__data_o
     connect \dmi1__ren \reg_1_dmi1__ren
     connect \dmi1__data_o \reg_1_dmi1__data_o
     connect \dest11__wen \reg_1_dest11__wen
     connect \dest11__data_i \reg_1_dest11__data_i
-    connect \dest21__wen \reg_1_dest21__wen
-    connect \dest21__data_i \reg_1_dest21__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_2_src12__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_src12__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_src22__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_src22__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_2_src32__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_src32__data_o
@@ -142498,35 +138453,23 @@ module \int
   wire width 1 \reg_2_dest12__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_dest12__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_dest22__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_dest22__data_i
   cell \reg_2 \reg_2
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src12__ren \reg_2_src12__ren
     connect \src12__data_o \reg_2_src12__data_o
-    connect \src22__ren \reg_2_src22__ren
-    connect \src22__data_o \reg_2_src22__data_o
     connect \src32__ren \reg_2_src32__ren
     connect \src32__data_o \reg_2_src32__data_o
     connect \dmi2__ren \reg_2_dmi2__ren
     connect \dmi2__data_o \reg_2_dmi2__data_o
     connect \dest12__wen \reg_2_dest12__wen
     connect \dest12__data_i \reg_2_dest12__data_i
-    connect \dest22__wen \reg_2_dest22__wen
-    connect \dest22__data_i \reg_2_dest22__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_3_src13__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_src13__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_src23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_src23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_3_src33__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_src33__data_o
@@ -142538,35 +138481,23 @@ module \int
   wire width 1 \reg_3_dest13__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_dest13__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_dest23__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_dest23__data_i
   cell \reg_3 \reg_3
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src13__ren \reg_3_src13__ren
     connect \src13__data_o \reg_3_src13__data_o
-    connect \src23__ren \reg_3_src23__ren
-    connect \src23__data_o \reg_3_src23__data_o
     connect \src33__ren \reg_3_src33__ren
     connect \src33__data_o \reg_3_src33__data_o
     connect \dmi3__ren \reg_3_dmi3__ren
     connect \dmi3__data_o \reg_3_dmi3__data_o
     connect \dest13__wen \reg_3_dest13__wen
     connect \dest13__data_i \reg_3_dest13__data_i
-    connect \dest23__wen \reg_3_dest23__wen
-    connect \dest23__data_i \reg_3_dest23__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_4_src14__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_src14__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_src24__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_src24__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_4_src34__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_src34__data_o
@@ -142578,35 +138509,23 @@ module \int
   wire width 1 \reg_4_dest14__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_dest14__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_dest24__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_dest24__data_i
   cell \reg_4 \reg_4
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src14__ren \reg_4_src14__ren
     connect \src14__data_o \reg_4_src14__data_o
-    connect \src24__ren \reg_4_src24__ren
-    connect \src24__data_o \reg_4_src24__data_o
     connect \src34__ren \reg_4_src34__ren
     connect \src34__data_o \reg_4_src34__data_o
     connect \dmi4__ren \reg_4_dmi4__ren
     connect \dmi4__data_o \reg_4_dmi4__data_o
     connect \dest14__wen \reg_4_dest14__wen
     connect \dest14__data_i \reg_4_dest14__data_i
-    connect \dest24__wen \reg_4_dest24__wen
-    connect \dest24__data_i \reg_4_dest24__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_5_src15__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_src15__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_src25__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_src25__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_5_src35__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_src35__data_o
@@ -142618,35 +138537,23 @@ module \int
   wire width 1 \reg_5_dest15__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_dest15__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_dest25__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_dest25__data_i
   cell \reg_5 \reg_5
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src15__ren \reg_5_src15__ren
     connect \src15__data_o \reg_5_src15__data_o
-    connect \src25__ren \reg_5_src25__ren
-    connect \src25__data_o \reg_5_src25__data_o
     connect \src35__ren \reg_5_src35__ren
     connect \src35__data_o \reg_5_src35__data_o
     connect \dmi5__ren \reg_5_dmi5__ren
     connect \dmi5__data_o \reg_5_dmi5__data_o
     connect \dest15__wen \reg_5_dest15__wen
     connect \dest15__data_i \reg_5_dest15__data_i
-    connect \dest25__wen \reg_5_dest25__wen
-    connect \dest25__data_i \reg_5_dest25__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_6_src16__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_src16__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_src26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_src26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_6_src36__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_src36__data_o
@@ -142658,35 +138565,23 @@ module \int
   wire width 1 \reg_6_dest16__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_dest16__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_dest26__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_dest26__data_i
   cell \reg_6 \reg_6
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src16__ren \reg_6_src16__ren
     connect \src16__data_o \reg_6_src16__data_o
-    connect \src26__ren \reg_6_src26__ren
-    connect \src26__data_o \reg_6_src26__data_o
     connect \src36__ren \reg_6_src36__ren
     connect \src36__data_o \reg_6_src36__data_o
     connect \dmi6__ren \reg_6_dmi6__ren
     connect \dmi6__data_o \reg_6_dmi6__data_o
     connect \dest16__wen \reg_6_dest16__wen
     connect \dest16__data_i \reg_6_dest16__data_i
-    connect \dest26__wen \reg_6_dest26__wen
-    connect \dest26__data_i \reg_6_dest26__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_7_src17__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_src17__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_src27__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_src27__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_7_src37__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_src37__data_o
@@ -142698,35 +138593,23 @@ module \int
   wire width 1 \reg_7_dest17__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_dest17__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_dest27__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_dest27__data_i
   cell \reg_7 \reg_7
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src17__ren \reg_7_src17__ren
     connect \src17__data_o \reg_7_src17__data_o
-    connect \src27__ren \reg_7_src27__ren
-    connect \src27__data_o \reg_7_src27__data_o
     connect \src37__ren \reg_7_src37__ren
     connect \src37__data_o \reg_7_src37__data_o
     connect \dmi7__ren \reg_7_dmi7__ren
     connect \dmi7__data_o \reg_7_dmi7__data_o
     connect \dest17__wen \reg_7_dest17__wen
     connect \dest17__data_i \reg_7_dest17__data_i
-    connect \dest27__wen \reg_7_dest27__wen
-    connect \dest27__data_i \reg_7_dest27__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_8_src18__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_src18__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_8_src28__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_8_src28__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_8_src38__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_src38__data_o
@@ -142738,35 +138621,23 @@ module \int
   wire width 1 \reg_8_dest18__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_dest18__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_8_dest28__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_8_dest28__data_i
   cell \reg_8 \reg_8
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src18__ren \reg_8_src18__ren
     connect \src18__data_o \reg_8_src18__data_o
-    connect \src28__ren \reg_8_src28__ren
-    connect \src28__data_o \reg_8_src28__data_o
     connect \src38__ren \reg_8_src38__ren
     connect \src38__data_o \reg_8_src38__data_o
     connect \dmi8__ren \reg_8_dmi8__ren
     connect \dmi8__data_o \reg_8_dmi8__data_o
     connect \dest18__wen \reg_8_dest18__wen
     connect \dest18__data_i \reg_8_dest18__data_i
-    connect \dest28__wen \reg_8_dest28__wen
-    connect \dest28__data_i \reg_8_dest28__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_9_src19__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_src19__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_9_src29__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_9_src29__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_9_src39__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_src39__data_o
@@ -142778,35 +138649,23 @@ module \int
   wire width 1 \reg_9_dest19__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_dest19__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_9_dest29__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_9_dest29__data_i
   cell \reg_9 \reg_9
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src19__ren \reg_9_src19__ren
     connect \src19__data_o \reg_9_src19__data_o
-    connect \src29__ren \reg_9_src29__ren
-    connect \src29__data_o \reg_9_src29__data_o
     connect \src39__ren \reg_9_src39__ren
     connect \src39__data_o \reg_9_src39__data_o
     connect \dmi9__ren \reg_9_dmi9__ren
     connect \dmi9__data_o \reg_9_dmi9__data_o
     connect \dest19__wen \reg_9_dest19__wen
     connect \dest19__data_i \reg_9_dest19__data_i
-    connect \dest29__wen \reg_9_dest29__wen
-    connect \dest29__data_i \reg_9_dest29__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_10_src110__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_src110__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_10_src210__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_10_src210__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_10_src310__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_src310__data_o
@@ -142818,35 +138677,23 @@ module \int
   wire width 1 \reg_10_dest110__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_dest110__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_10_dest210__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_10_dest210__data_i
   cell \reg_10 \reg_10
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src110__ren \reg_10_src110__ren
     connect \src110__data_o \reg_10_src110__data_o
-    connect \src210__ren \reg_10_src210__ren
-    connect \src210__data_o \reg_10_src210__data_o
     connect \src310__ren \reg_10_src310__ren
     connect \src310__data_o \reg_10_src310__data_o
     connect \dmi10__ren \reg_10_dmi10__ren
     connect \dmi10__data_o \reg_10_dmi10__data_o
     connect \dest110__wen \reg_10_dest110__wen
     connect \dest110__data_i \reg_10_dest110__data_i
-    connect \dest210__wen \reg_10_dest210__wen
-    connect \dest210__data_i \reg_10_dest210__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_11_src111__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_src111__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_11_src211__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_11_src211__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_11_src311__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_src311__data_o
@@ -142858,35 +138705,23 @@ module \int
   wire width 1 \reg_11_dest111__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_dest111__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_11_dest211__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_11_dest211__data_i
   cell \reg_11 \reg_11
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src111__ren \reg_11_src111__ren
     connect \src111__data_o \reg_11_src111__data_o
-    connect \src211__ren \reg_11_src211__ren
-    connect \src211__data_o \reg_11_src211__data_o
     connect \src311__ren \reg_11_src311__ren
     connect \src311__data_o \reg_11_src311__data_o
     connect \dmi11__ren \reg_11_dmi11__ren
     connect \dmi11__data_o \reg_11_dmi11__data_o
     connect \dest111__wen \reg_11_dest111__wen
     connect \dest111__data_i \reg_11_dest111__data_i
-    connect \dest211__wen \reg_11_dest211__wen
-    connect \dest211__data_i \reg_11_dest211__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_12_src112__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_src112__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_12_src212__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_12_src212__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_12_src312__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_src312__data_o
@@ -142898,35 +138733,23 @@ module \int
   wire width 1 \reg_12_dest112__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_dest112__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_12_dest212__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_12_dest212__data_i
   cell \reg_12 \reg_12
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src112__ren \reg_12_src112__ren
     connect \src112__data_o \reg_12_src112__data_o
-    connect \src212__ren \reg_12_src212__ren
-    connect \src212__data_o \reg_12_src212__data_o
     connect \src312__ren \reg_12_src312__ren
     connect \src312__data_o \reg_12_src312__data_o
     connect \dmi12__ren \reg_12_dmi12__ren
     connect \dmi12__data_o \reg_12_dmi12__data_o
     connect \dest112__wen \reg_12_dest112__wen
     connect \dest112__data_i \reg_12_dest112__data_i
-    connect \dest212__wen \reg_12_dest212__wen
-    connect \dest212__data_i \reg_12_dest212__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_13_src113__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_src113__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_13_src213__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_13_src213__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_13_src313__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_src313__data_o
@@ -142938,35 +138761,23 @@ module \int
   wire width 1 \reg_13_dest113__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_dest113__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_13_dest213__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_13_dest213__data_i
   cell \reg_13 \reg_13
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src113__ren \reg_13_src113__ren
     connect \src113__data_o \reg_13_src113__data_o
-    connect \src213__ren \reg_13_src213__ren
-    connect \src213__data_o \reg_13_src213__data_o
     connect \src313__ren \reg_13_src313__ren
     connect \src313__data_o \reg_13_src313__data_o
     connect \dmi13__ren \reg_13_dmi13__ren
     connect \dmi13__data_o \reg_13_dmi13__data_o
     connect \dest113__wen \reg_13_dest113__wen
     connect \dest113__data_i \reg_13_dest113__data_i
-    connect \dest213__wen \reg_13_dest213__wen
-    connect \dest213__data_i \reg_13_dest213__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_14_src114__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_src114__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_14_src214__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_14_src214__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_14_src314__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_src314__data_o
@@ -142978,35 +138789,23 @@ module \int
   wire width 1 \reg_14_dest114__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_dest114__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_14_dest214__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_14_dest214__data_i
   cell \reg_14 \reg_14
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src114__ren \reg_14_src114__ren
     connect \src114__data_o \reg_14_src114__data_o
-    connect \src214__ren \reg_14_src214__ren
-    connect \src214__data_o \reg_14_src214__data_o
     connect \src314__ren \reg_14_src314__ren
     connect \src314__data_o \reg_14_src314__data_o
     connect \dmi14__ren \reg_14_dmi14__ren
     connect \dmi14__data_o \reg_14_dmi14__data_o
     connect \dest114__wen \reg_14_dest114__wen
     connect \dest114__data_i \reg_14_dest114__data_i
-    connect \dest214__wen \reg_14_dest214__wen
-    connect \dest214__data_i \reg_14_dest214__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_15_src115__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_src115__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_15_src215__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_15_src215__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_15_src315__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_src315__data_o
@@ -143018,35 +138817,23 @@ module \int
   wire width 1 \reg_15_dest115__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_dest115__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_15_dest215__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_15_dest215__data_i
   cell \reg_15 \reg_15
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src115__ren \reg_15_src115__ren
     connect \src115__data_o \reg_15_src115__data_o
-    connect \src215__ren \reg_15_src215__ren
-    connect \src215__data_o \reg_15_src215__data_o
     connect \src315__ren \reg_15_src315__ren
     connect \src315__data_o \reg_15_src315__data_o
     connect \dmi15__ren \reg_15_dmi15__ren
     connect \dmi15__data_o \reg_15_dmi15__data_o
     connect \dest115__wen \reg_15_dest115__wen
     connect \dest115__data_i \reg_15_dest115__data_i
-    connect \dest215__wen \reg_15_dest215__wen
-    connect \dest215__data_i \reg_15_dest215__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_16_src116__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_src116__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_16_src216__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_16_src216__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_16_src316__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_src316__data_o
@@ -143058,35 +138845,23 @@ module \int
   wire width 1 \reg_16_dest116__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_dest116__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_16_dest216__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_16_dest216__data_i
   cell \reg_16 \reg_16
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src116__ren \reg_16_src116__ren
     connect \src116__data_o \reg_16_src116__data_o
-    connect \src216__ren \reg_16_src216__ren
-    connect \src216__data_o \reg_16_src216__data_o
     connect \src316__ren \reg_16_src316__ren
     connect \src316__data_o \reg_16_src316__data_o
     connect \dmi16__ren \reg_16_dmi16__ren
     connect \dmi16__data_o \reg_16_dmi16__data_o
     connect \dest116__wen \reg_16_dest116__wen
     connect \dest116__data_i \reg_16_dest116__data_i
-    connect \dest216__wen \reg_16_dest216__wen
-    connect \dest216__data_i \reg_16_dest216__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_17_src117__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_src117__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_17_src217__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_17_src217__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_17_src317__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_src317__data_o
@@ -143098,35 +138873,23 @@ module \int
   wire width 1 \reg_17_dest117__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_dest117__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_17_dest217__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_17_dest217__data_i
   cell \reg_17 \reg_17
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src117__ren \reg_17_src117__ren
     connect \src117__data_o \reg_17_src117__data_o
-    connect \src217__ren \reg_17_src217__ren
-    connect \src217__data_o \reg_17_src217__data_o
     connect \src317__ren \reg_17_src317__ren
     connect \src317__data_o \reg_17_src317__data_o
     connect \dmi17__ren \reg_17_dmi17__ren
     connect \dmi17__data_o \reg_17_dmi17__data_o
     connect \dest117__wen \reg_17_dest117__wen
     connect \dest117__data_i \reg_17_dest117__data_i
-    connect \dest217__wen \reg_17_dest217__wen
-    connect \dest217__data_i \reg_17_dest217__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_18_src118__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_src118__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_18_src218__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_18_src218__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_18_src318__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_src318__data_o
@@ -143138,35 +138901,23 @@ module \int
   wire width 1 \reg_18_dest118__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_dest118__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_18_dest218__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_18_dest218__data_i
   cell \reg_18 \reg_18
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src118__ren \reg_18_src118__ren
     connect \src118__data_o \reg_18_src118__data_o
-    connect \src218__ren \reg_18_src218__ren
-    connect \src218__data_o \reg_18_src218__data_o
     connect \src318__ren \reg_18_src318__ren
     connect \src318__data_o \reg_18_src318__data_o
     connect \dmi18__ren \reg_18_dmi18__ren
     connect \dmi18__data_o \reg_18_dmi18__data_o
     connect \dest118__wen \reg_18_dest118__wen
     connect \dest118__data_i \reg_18_dest118__data_i
-    connect \dest218__wen \reg_18_dest218__wen
-    connect \dest218__data_i \reg_18_dest218__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_19_src119__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_src119__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_19_src219__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_19_src219__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_19_src319__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_src319__data_o
@@ -143178,35 +138929,23 @@ module \int
   wire width 1 \reg_19_dest119__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_dest119__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_19_dest219__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_19_dest219__data_i
   cell \reg_19 \reg_19
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src119__ren \reg_19_src119__ren
     connect \src119__data_o \reg_19_src119__data_o
-    connect \src219__ren \reg_19_src219__ren
-    connect \src219__data_o \reg_19_src219__data_o
     connect \src319__ren \reg_19_src319__ren
     connect \src319__data_o \reg_19_src319__data_o
     connect \dmi19__ren \reg_19_dmi19__ren
     connect \dmi19__data_o \reg_19_dmi19__data_o
     connect \dest119__wen \reg_19_dest119__wen
     connect \dest119__data_i \reg_19_dest119__data_i
-    connect \dest219__wen \reg_19_dest219__wen
-    connect \dest219__data_i \reg_19_dest219__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_20_src120__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_src120__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_20_src220__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_20_src220__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_20_src320__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_src320__data_o
@@ -143218,35 +138957,23 @@ module \int
   wire width 1 \reg_20_dest120__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_dest120__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_20_dest220__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_20_dest220__data_i
   cell \reg_20 \reg_20
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src120__ren \reg_20_src120__ren
     connect \src120__data_o \reg_20_src120__data_o
-    connect \src220__ren \reg_20_src220__ren
-    connect \src220__data_o \reg_20_src220__data_o
     connect \src320__ren \reg_20_src320__ren
     connect \src320__data_o \reg_20_src320__data_o
     connect \dmi20__ren \reg_20_dmi20__ren
     connect \dmi20__data_o \reg_20_dmi20__data_o
     connect \dest120__wen \reg_20_dest120__wen
     connect \dest120__data_i \reg_20_dest120__data_i
-    connect \dest220__wen \reg_20_dest220__wen
-    connect \dest220__data_i \reg_20_dest220__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_21_src121__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_src121__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_21_src221__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_21_src221__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_21_src321__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_src321__data_o
@@ -143258,35 +138985,23 @@ module \int
   wire width 1 \reg_21_dest121__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_dest121__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_21_dest221__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_21_dest221__data_i
   cell \reg_21 \reg_21
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src121__ren \reg_21_src121__ren
     connect \src121__data_o \reg_21_src121__data_o
-    connect \src221__ren \reg_21_src221__ren
-    connect \src221__data_o \reg_21_src221__data_o
     connect \src321__ren \reg_21_src321__ren
     connect \src321__data_o \reg_21_src321__data_o
     connect \dmi21__ren \reg_21_dmi21__ren
     connect \dmi21__data_o \reg_21_dmi21__data_o
     connect \dest121__wen \reg_21_dest121__wen
     connect \dest121__data_i \reg_21_dest121__data_i
-    connect \dest221__wen \reg_21_dest221__wen
-    connect \dest221__data_i \reg_21_dest221__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_22_src122__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_src122__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_22_src222__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_22_src222__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_22_src322__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_src322__data_o
@@ -143298,35 +139013,23 @@ module \int
   wire width 1 \reg_22_dest122__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_dest122__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_22_dest222__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_22_dest222__data_i
   cell \reg_22 \reg_22
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src122__ren \reg_22_src122__ren
     connect \src122__data_o \reg_22_src122__data_o
-    connect \src222__ren \reg_22_src222__ren
-    connect \src222__data_o \reg_22_src222__data_o
     connect \src322__ren \reg_22_src322__ren
     connect \src322__data_o \reg_22_src322__data_o
     connect \dmi22__ren \reg_22_dmi22__ren
     connect \dmi22__data_o \reg_22_dmi22__data_o
     connect \dest122__wen \reg_22_dest122__wen
     connect \dest122__data_i \reg_22_dest122__data_i
-    connect \dest222__wen \reg_22_dest222__wen
-    connect \dest222__data_i \reg_22_dest222__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_23_src123__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_src123__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_23_src223__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_23_src223__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_23_src323__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_src323__data_o
@@ -143338,35 +139041,23 @@ module \int
   wire width 1 \reg_23_dest123__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_dest123__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_23_dest223__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_23_dest223__data_i
   cell \reg_23 \reg_23
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src123__ren \reg_23_src123__ren
     connect \src123__data_o \reg_23_src123__data_o
-    connect \src223__ren \reg_23_src223__ren
-    connect \src223__data_o \reg_23_src223__data_o
     connect \src323__ren \reg_23_src323__ren
     connect \src323__data_o \reg_23_src323__data_o
     connect \dmi23__ren \reg_23_dmi23__ren
     connect \dmi23__data_o \reg_23_dmi23__data_o
     connect \dest123__wen \reg_23_dest123__wen
     connect \dest123__data_i \reg_23_dest123__data_i
-    connect \dest223__wen \reg_23_dest223__wen
-    connect \dest223__data_i \reg_23_dest223__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_24_src124__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_src124__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_24_src224__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_24_src224__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_24_src324__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_src324__data_o
@@ -143378,35 +139069,23 @@ module \int
   wire width 1 \reg_24_dest124__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_dest124__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_24_dest224__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_24_dest224__data_i
   cell \reg_24 \reg_24
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src124__ren \reg_24_src124__ren
     connect \src124__data_o \reg_24_src124__data_o
-    connect \src224__ren \reg_24_src224__ren
-    connect \src224__data_o \reg_24_src224__data_o
     connect \src324__ren \reg_24_src324__ren
     connect \src324__data_o \reg_24_src324__data_o
     connect \dmi24__ren \reg_24_dmi24__ren
     connect \dmi24__data_o \reg_24_dmi24__data_o
     connect \dest124__wen \reg_24_dest124__wen
     connect \dest124__data_i \reg_24_dest124__data_i
-    connect \dest224__wen \reg_24_dest224__wen
-    connect \dest224__data_i \reg_24_dest224__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_25_src125__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_src125__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_25_src225__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_25_src225__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_25_src325__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_src325__data_o
@@ -143418,35 +139097,23 @@ module \int
   wire width 1 \reg_25_dest125__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_dest125__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_25_dest225__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_25_dest225__data_i
   cell \reg_25 \reg_25
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src125__ren \reg_25_src125__ren
     connect \src125__data_o \reg_25_src125__data_o
-    connect \src225__ren \reg_25_src225__ren
-    connect \src225__data_o \reg_25_src225__data_o
     connect \src325__ren \reg_25_src325__ren
     connect \src325__data_o \reg_25_src325__data_o
     connect \dmi25__ren \reg_25_dmi25__ren
     connect \dmi25__data_o \reg_25_dmi25__data_o
     connect \dest125__wen \reg_25_dest125__wen
     connect \dest125__data_i \reg_25_dest125__data_i
-    connect \dest225__wen \reg_25_dest225__wen
-    connect \dest225__data_i \reg_25_dest225__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_26_src126__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_src126__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_26_src226__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_26_src226__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_26_src326__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_src326__data_o
@@ -143458,35 +139125,23 @@ module \int
   wire width 1 \reg_26_dest126__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_dest126__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_26_dest226__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_26_dest226__data_i
   cell \reg_26 \reg_26
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src126__ren \reg_26_src126__ren
     connect \src126__data_o \reg_26_src126__data_o
-    connect \src226__ren \reg_26_src226__ren
-    connect \src226__data_o \reg_26_src226__data_o
     connect \src326__ren \reg_26_src326__ren
     connect \src326__data_o \reg_26_src326__data_o
     connect \dmi26__ren \reg_26_dmi26__ren
     connect \dmi26__data_o \reg_26_dmi26__data_o
     connect \dest126__wen \reg_26_dest126__wen
     connect \dest126__data_i \reg_26_dest126__data_i
-    connect \dest226__wen \reg_26_dest226__wen
-    connect \dest226__data_i \reg_26_dest226__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_27_src127__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_src127__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_27_src227__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_27_src227__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_27_src327__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_src327__data_o
@@ -143498,35 +139153,23 @@ module \int
   wire width 1 \reg_27_dest127__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_dest127__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_27_dest227__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_27_dest227__data_i
   cell \reg_27 \reg_27
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src127__ren \reg_27_src127__ren
     connect \src127__data_o \reg_27_src127__data_o
-    connect \src227__ren \reg_27_src227__ren
-    connect \src227__data_o \reg_27_src227__data_o
     connect \src327__ren \reg_27_src327__ren
     connect \src327__data_o \reg_27_src327__data_o
     connect \dmi27__ren \reg_27_dmi27__ren
     connect \dmi27__data_o \reg_27_dmi27__data_o
     connect \dest127__wen \reg_27_dest127__wen
     connect \dest127__data_i \reg_27_dest127__data_i
-    connect \dest227__wen \reg_27_dest227__wen
-    connect \dest227__data_i \reg_27_dest227__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_28_src128__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_src128__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_28_src228__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_28_src228__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_28_src328__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_src328__data_o
@@ -143538,35 +139181,23 @@ module \int
   wire width 1 \reg_28_dest128__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_dest128__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_28_dest228__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_28_dest228__data_i
   cell \reg_28 \reg_28
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src128__ren \reg_28_src128__ren
     connect \src128__data_o \reg_28_src128__data_o
-    connect \src228__ren \reg_28_src228__ren
-    connect \src228__data_o \reg_28_src228__data_o
     connect \src328__ren \reg_28_src328__ren
     connect \src328__data_o \reg_28_src328__data_o
     connect \dmi28__ren \reg_28_dmi28__ren
     connect \dmi28__data_o \reg_28_dmi28__data_o
     connect \dest128__wen \reg_28_dest128__wen
     connect \dest128__data_i \reg_28_dest128__data_i
-    connect \dest228__wen \reg_28_dest228__wen
-    connect \dest228__data_i \reg_28_dest228__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_29_src129__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_src129__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_29_src229__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_29_src229__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_29_src329__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_src329__data_o
@@ -143578,35 +139209,23 @@ module \int
   wire width 1 \reg_29_dest129__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_dest129__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_29_dest229__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_29_dest229__data_i
   cell \reg_29 \reg_29
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src129__ren \reg_29_src129__ren
     connect \src129__data_o \reg_29_src129__data_o
-    connect \src229__ren \reg_29_src229__ren
-    connect \src229__data_o \reg_29_src229__data_o
     connect \src329__ren \reg_29_src329__ren
     connect \src329__data_o \reg_29_src329__data_o
     connect \dmi29__ren \reg_29_dmi29__ren
     connect \dmi29__data_o \reg_29_dmi29__data_o
     connect \dest129__wen \reg_29_dest129__wen
     connect \dest129__data_i \reg_29_dest129__data_i
-    connect \dest229__wen \reg_29_dest229__wen
-    connect \dest229__data_i \reg_29_dest229__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_30_src130__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_src130__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_30_src230__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_30_src230__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_30_src330__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_src330__data_o
@@ -143618,35 +139237,23 @@ module \int
   wire width 1 \reg_30_dest130__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_dest130__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_30_dest230__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_30_dest230__data_i
   cell \reg_30 \reg_30
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src130__ren \reg_30_src130__ren
     connect \src130__data_o \reg_30_src130__data_o
-    connect \src230__ren \reg_30_src230__ren
-    connect \src230__data_o \reg_30_src230__data_o
     connect \src330__ren \reg_30_src330__ren
     connect \src330__data_o \reg_30_src330__data_o
     connect \dmi30__ren \reg_30_dmi30__ren
     connect \dmi30__data_o \reg_30_dmi30__data_o
     connect \dest130__wen \reg_30_dest130__wen
     connect \dest130__data_i \reg_30_dest130__data_i
-    connect \dest230__wen \reg_30_dest230__wen
-    connect \dest230__data_i \reg_30_dest230__data_i
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_31_src131__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_src131__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_31_src231__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_31_src231__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_31_src331__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_src331__data_o
@@ -143658,25 +139265,17 @@ module \int
   wire width 1 \reg_31_dest131__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_dest131__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_31_dest231__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_31_dest231__data_i
   cell \reg_31 \reg_31
     connect \coresync_clk \coresync_clk
     connect \coresync_rst \coresync_rst
     connect \src131__ren \reg_31_src131__ren
     connect \src131__data_o \reg_31_src131__data_o
-    connect \src231__ren \reg_31_src231__ren
-    connect \src231__data_o \reg_31_src231__data_o
     connect \src331__ren \reg_31_src331__ren
     connect \src331__data_o \reg_31_src331__data_o
     connect \dmi31__ren \reg_31_dmi31__ren
     connect \dmi31__data_o \reg_31_dmi31__data_o
     connect \dest131__wen \reg_31_dest131__wen
     connect \dest131__data_i \reg_31_dest131__data_i
-    connect \dest231__wen \reg_31_dest231__wen
-    connect \dest231__data_i \reg_31_dest231__data_i
   end
   process $group_0
     assign \reg_0_src10__ren 1'0
@@ -143715,9 +139314,9 @@ module \int
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $3
+  wire width 64 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $4
+  cell $or $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -143725,12 +139324,12 @@ module \int
     parameter \Y_WIDTH 64
     connect \A \reg_0_src10__data_o
     connect \B \reg_1_src11__data_o
-    connect \Y $3
+    connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $5
+  wire width 64 $3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $6
+  cell $or $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -143738,19 +139337,32 @@ module \int
     parameter \Y_WIDTH 64
     connect \A \reg_2_src12__data_o
     connect \B \reg_3_src13__data_o
-    connect \Y $5
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $7
+  wire width 64 $5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $1
+    connect \B $3
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $3
-    connect \B $5
+    connect \A \reg_4_src14__data_o
+    connect \B \reg_5_src15__data_o
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -143762,21 +139374,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_4_src14__data_o
-    connect \B \reg_5_src15__data_o
+    connect \A \reg_6_src16__data_o
+    connect \B \reg_7_src17__data_o
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_6_src16__data_o
-    connect \B \reg_7_src17__data_o
+    connect \A $7
+    connect \B $9
     connect \Y $11
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -143788,21 +139400,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $9
+    connect \A $5
     connect \B $11
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $7
-    connect \B $13
+    connect \A \reg_8_src18__data_o
+    connect \B \reg_9_src19__data_o
     connect \Y $15
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -143814,34 +139426,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_8_src18__data_o
-    connect \B \reg_9_src19__data_o
+    connect \A \reg_10_src110__data_o
+    connect \B \reg_11_src111__data_o
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $19
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_10_src110__data_o
-    connect \B \reg_11_src111__data_o
+    connect \A $15
+    connect \B $17
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $21
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $17
-    connect \B $19
+    connect \A \reg_12_src112__data_o
+    connect \B \reg_13_src113__data_o
     connect \Y $21
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -143853,21 +139465,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_12_src112__data_o
-    connect \B \reg_13_src113__data_o
+    connect \A \reg_14_src114__data_o
+    connect \B \reg_15_src115__data_o
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $25
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_14_src114__data_o
-    connect \B \reg_15_src115__data_o
+    connect \A $21
+    connect \B $23
     connect \Y $25
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -143879,7 +139491,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $23
+    connect \A $19
     connect \B $25
     connect \Y $27
   end
@@ -143892,21 +139504,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $21
+    connect \A $13
     connect \B $27
     connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $31
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $15
-    connect \B $29
+    connect \A \reg_16_src116__data_o
+    connect \B \reg_17_src117__data_o
     connect \Y $31
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -143918,34 +139530,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_16_src116__data_o
-    connect \B \reg_17_src117__data_o
+    connect \A \reg_18_src118__data_o
+    connect \B \reg_19_src119__data_o
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $35
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_18_src118__data_o
-    connect \B \reg_19_src119__data_o
+    connect \A $31
+    connect \B $33
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $37
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $33
-    connect \B $35
+    connect \A \reg_20_src120__data_o
+    connect \B \reg_21_src121__data_o
     connect \Y $37
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -143957,21 +139569,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_20_src120__data_o
-    connect \B \reg_21_src121__data_o
+    connect \A \reg_22_src122__data_o
+    connect \B \reg_23_src123__data_o
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $41
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_22_src122__data_o
-    connect \B \reg_23_src123__data_o
+    connect \A $37
+    connect \B $39
     connect \Y $41
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -143983,21 +139595,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $39
+    connect \A $35
     connect \B $41
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $45
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $37
-    connect \B $43
+    connect \A \reg_24_src124__data_o
+    connect \B \reg_25_src125__data_o
     connect \Y $45
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144009,34 +139621,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_24_src124__data_o
-    connect \B \reg_25_src125__data_o
+    connect \A \reg_26_src126__data_o
+    connect \B \reg_27_src127__data_o
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $49
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_26_src126__data_o
-    connect \B \reg_27_src127__data_o
+    connect \A $45
+    connect \B $47
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $51
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $47
-    connect \B $49
+    connect \A \reg_28_src128__data_o
+    connect \B \reg_29_src129__data_o
     connect \Y $51
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144048,21 +139660,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_28_src128__data_o
-    connect \B \reg_29_src129__data_o
+    connect \A \reg_30_src130__data_o
+    connect \B \reg_31_src131__data_o
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $55
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_30_src130__data_o
-    connect \B \reg_31_src131__data_o
+    connect \A $51
+    connect \B $53
     connect \Y $55
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144074,7 +139686,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $53
+    connect \A $49
     connect \B $55
     connect \Y $57
   end
@@ -144087,7 +139699,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $51
+    connect \A $43
     connect \B $57
     connect \Y $59
   end
@@ -144100,64 +139712,64 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $45
+    connect \A $29
     connect \B $59
     connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  process $group_32
+    assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1__data_o $61
+    sync init
+  end
+  process $group_33
+    assign \reg_0_src30__ren 1'0
+    assign \reg_1_src31__ren 1'0
+    assign \reg_2_src32__ren 1'0
+    assign \reg_3_src33__ren 1'0
+    assign \reg_4_src34__ren 1'0
+    assign \reg_5_src35__ren 1'0
+    assign \reg_6_src36__ren 1'0
+    assign \reg_7_src37__ren 1'0
+    assign \reg_8_src38__ren 1'0
+    assign \reg_9_src39__ren 1'0
+    assign \reg_10_src310__ren 1'0
+    assign \reg_11_src311__ren 1'0
+    assign \reg_12_src312__ren 1'0
+    assign \reg_13_src313__ren 1'0
+    assign \reg_14_src314__ren 1'0
+    assign \reg_15_src315__ren 1'0
+    assign \reg_16_src316__ren 1'0
+    assign \reg_17_src317__ren 1'0
+    assign \reg_18_src318__ren 1'0
+    assign \reg_19_src319__ren 1'0
+    assign \reg_20_src320__ren 1'0
+    assign \reg_21_src321__ren 1'0
+    assign \reg_22_src322__ren 1'0
+    assign \reg_23_src323__ren 1'0
+    assign \reg_24_src324__ren 1'0
+    assign \reg_25_src325__ren 1'0
+    assign \reg_26_src326__ren 1'0
+    assign \reg_27_src327__ren 1'0
+    assign \reg_28_src328__ren 1'0
+    assign \reg_29_src329__ren 1'0
+    assign \reg_30_src330__ren 1'0
+    assign \reg_31_src331__ren 1'0
+    assign { \reg_31_src331__ren \reg_30_src330__ren \reg_29_src329__ren \reg_28_src328__ren \reg_27_src327__ren \reg_26_src326__ren \reg_25_src325__ren \reg_24_src324__ren \reg_23_src323__ren \reg_22_src322__ren \reg_21_src321__ren \reg_20_src320__ren \reg_19_src319__ren \reg_18_src318__ren \reg_17_src317__ren \reg_16_src316__ren \reg_15_src315__ren \reg_14_src314__ren \reg_13_src313__ren \reg_12_src312__ren \reg_11_src311__ren \reg_10_src310__ren \reg_9_src39__ren \reg_8_src38__ren \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $63
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $31
-    connect \B $61
+    connect \A \reg_0_src30__data_o
+    connect \B \reg_1_src31__data_o
     connect \Y $63
   end
-  process $group_32
-    assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1__data_o $63
-    sync init
-  end
-  process $group_33
-    assign \reg_0_src20__ren 1'0
-    assign \reg_1_src21__ren 1'0
-    assign \reg_2_src22__ren 1'0
-    assign \reg_3_src23__ren 1'0
-    assign \reg_4_src24__ren 1'0
-    assign \reg_5_src25__ren 1'0
-    assign \reg_6_src26__ren 1'0
-    assign \reg_7_src27__ren 1'0
-    assign \reg_8_src28__ren 1'0
-    assign \reg_9_src29__ren 1'0
-    assign \reg_10_src210__ren 1'0
-    assign \reg_11_src211__ren 1'0
-    assign \reg_12_src212__ren 1'0
-    assign \reg_13_src213__ren 1'0
-    assign \reg_14_src214__ren 1'0
-    assign \reg_15_src215__ren 1'0
-    assign \reg_16_src216__ren 1'0
-    assign \reg_17_src217__ren 1'0
-    assign \reg_18_src218__ren 1'0
-    assign \reg_19_src219__ren 1'0
-    assign \reg_20_src220__ren 1'0
-    assign \reg_21_src221__ren 1'0
-    assign \reg_22_src222__ren 1'0
-    assign \reg_23_src223__ren 1'0
-    assign \reg_24_src224__ren 1'0
-    assign \reg_25_src225__ren 1'0
-    assign \reg_26_src226__ren 1'0
-    assign \reg_27_src227__ren 1'0
-    assign \reg_28_src228__ren 1'0
-    assign \reg_29_src229__ren 1'0
-    assign \reg_30_src230__ren 1'0
-    assign \reg_31_src231__ren 1'0
-    assign { \reg_31_src231__ren \reg_30_src230__ren \reg_29_src229__ren \reg_28_src228__ren \reg_27_src227__ren \reg_26_src226__ren \reg_25_src225__ren \reg_24_src224__ren \reg_23_src223__ren \reg_22_src222__ren \reg_21_src221__ren \reg_20_src220__ren \reg_19_src219__ren \reg_18_src218__ren \reg_17_src217__ren \reg_16_src216__ren \reg_15_src215__ren \reg_14_src214__ren \reg_13_src213__ren \reg_12_src212__ren \reg_11_src211__ren \reg_10_src210__ren \reg_9_src29__ren \reg_8_src28__ren \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
-    sync init
-  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $65
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144167,34 +139779,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_0_src20__data_o
-    connect \B \reg_1_src21__data_o
+    connect \A \reg_2_src32__data_o
+    connect \B \reg_3_src33__data_o
     connect \Y $65
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $67
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_2_src22__data_o
-    connect \B \reg_3_src23__data_o
+    connect \A $63
+    connect \B $65
     connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $69
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $65
-    connect \B $67
+    connect \A \reg_4_src34__data_o
+    connect \B \reg_5_src35__data_o
     connect \Y $69
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144206,21 +139818,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_4_src24__data_o
-    connect \B \reg_5_src25__data_o
-    connect \Y $71
+    connect \A \reg_6_src36__data_o
+    connect \B \reg_7_src37__data_o
+    connect \Y $71
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $73
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_6_src26__data_o
-    connect \B \reg_7_src27__data_o
+    connect \A $69
+    connect \B $71
     connect \Y $73
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144232,21 +139844,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $71
+    connect \A $67
     connect \B $73
     connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $77
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $69
-    connect \B $75
+    connect \A \reg_8_src38__data_o
+    connect \B \reg_9_src39__data_o
     connect \Y $77
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144258,34 +139870,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_8_src28__data_o
-    connect \B \reg_9_src29__data_o
+    connect \A \reg_10_src310__data_o
+    connect \B \reg_11_src311__data_o
     connect \Y $79
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $81
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_10_src210__data_o
-    connect \B \reg_11_src211__data_o
+    connect \A $77
+    connect \B $79
     connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $83
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $79
-    connect \B $81
+    connect \A \reg_12_src312__data_o
+    connect \B \reg_13_src313__data_o
     connect \Y $83
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144297,21 +139909,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_12_src212__data_o
-    connect \B \reg_13_src213__data_o
+    connect \A \reg_14_src314__data_o
+    connect \B \reg_15_src315__data_o
     connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $87
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_14_src214__data_o
-    connect \B \reg_15_src215__data_o
+    connect \A $83
+    connect \B $85
     connect \Y $87
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144323,7 +139935,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $85
+    connect \A $81
     connect \B $87
     connect \Y $89
   end
@@ -144336,21 +139948,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $83
+    connect \A $75
     connect \B $89
     connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $93
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $77
-    connect \B $91
+    connect \A \reg_16_src316__data_o
+    connect \B \reg_17_src317__data_o
     connect \Y $93
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144362,34 +139974,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_16_src216__data_o
-    connect \B \reg_17_src217__data_o
+    connect \A \reg_18_src318__data_o
+    connect \B \reg_19_src319__data_o
     connect \Y $95
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $97
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $98
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_18_src218__data_o
-    connect \B \reg_19_src219__data_o
+    connect \A $93
+    connect \B $95
     connect \Y $97
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $99
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $95
-    connect \B $97
+    connect \A \reg_20_src320__data_o
+    connect \B \reg_21_src321__data_o
     connect \Y $99
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144401,21 +140013,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_20_src220__data_o
-    connect \B \reg_21_src221__data_o
+    connect \A \reg_22_src322__data_o
+    connect \B \reg_23_src323__data_o
     connect \Y $101
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $103
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_22_src222__data_o
-    connect \B \reg_23_src223__data_o
+    connect \A $99
+    connect \B $101
     connect \Y $103
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144427,21 +140039,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $101
+    connect \A $97
     connect \B $103
     connect \Y $105
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $107
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $99
-    connect \B $105
+    connect \A \reg_24_src324__data_o
+    connect \B \reg_25_src325__data_o
     connect \Y $107
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144453,34 +140065,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_24_src224__data_o
-    connect \B \reg_25_src225__data_o
+    connect \A \reg_26_src326__data_o
+    connect \B \reg_27_src327__data_o
     connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $111
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_26_src226__data_o
-    connect \B \reg_27_src227__data_o
+    connect \A $107
+    connect \B $109
     connect \Y $111
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $113
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $109
-    connect \B $111
+    connect \A \reg_28_src328__data_o
+    connect \B \reg_29_src329__data_o
     connect \Y $113
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144492,21 +140104,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_28_src228__data_o
-    connect \B \reg_29_src229__data_o
+    connect \A \reg_30_src330__data_o
+    connect \B \reg_31_src331__data_o
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $117
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_30_src230__data_o
-    connect \B \reg_31_src231__data_o
+    connect \A $113
+    connect \B $115
     connect \Y $117
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144518,7 +140130,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $115
+    connect \A $111
     connect \B $117
     connect \Y $119
   end
@@ -144531,7 +140143,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $113
+    connect \A $105
     connect \B $119
     connect \Y $121
   end
@@ -144544,64 +140156,64 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $107
+    connect \A $91
     connect \B $121
     connect \Y $123
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  process $group_65
+    assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src3__data_o $123
+    sync init
+  end
+  process $group_66
+    assign \reg_0_dmi0__ren 1'0
+    assign \reg_1_dmi1__ren 1'0
+    assign \reg_2_dmi2__ren 1'0
+    assign \reg_3_dmi3__ren 1'0
+    assign \reg_4_dmi4__ren 1'0
+    assign \reg_5_dmi5__ren 1'0
+    assign \reg_6_dmi6__ren 1'0
+    assign \reg_7_dmi7__ren 1'0
+    assign \reg_8_dmi8__ren 1'0
+    assign \reg_9_dmi9__ren 1'0
+    assign \reg_10_dmi10__ren 1'0
+    assign \reg_11_dmi11__ren 1'0
+    assign \reg_12_dmi12__ren 1'0
+    assign \reg_13_dmi13__ren 1'0
+    assign \reg_14_dmi14__ren 1'0
+    assign \reg_15_dmi15__ren 1'0
+    assign \reg_16_dmi16__ren 1'0
+    assign \reg_17_dmi17__ren 1'0
+    assign \reg_18_dmi18__ren 1'0
+    assign \reg_19_dmi19__ren 1'0
+    assign \reg_20_dmi20__ren 1'0
+    assign \reg_21_dmi21__ren 1'0
+    assign \reg_22_dmi22__ren 1'0
+    assign \reg_23_dmi23__ren 1'0
+    assign \reg_24_dmi24__ren 1'0
+    assign \reg_25_dmi25__ren 1'0
+    assign \reg_26_dmi26__ren 1'0
+    assign \reg_27_dmi27__ren 1'0
+    assign \reg_28_dmi28__ren 1'0
+    assign \reg_29_dmi29__ren 1'0
+    assign \reg_30_dmi30__ren 1'0
+    assign \reg_31_dmi31__ren 1'0
+    assign { \reg_31_dmi31__ren \reg_30_dmi30__ren \reg_29_dmi29__ren \reg_28_dmi28__ren \reg_27_dmi27__ren \reg_26_dmi26__ren \reg_25_dmi25__ren \reg_24_dmi24__ren \reg_23_dmi23__ren \reg_22_dmi22__ren \reg_21_dmi21__ren \reg_20_dmi20__ren \reg_19_dmi19__ren \reg_18_dmi18__ren \reg_17_dmi17__ren \reg_16_dmi16__ren \reg_15_dmi15__ren \reg_14_dmi14__ren \reg_13_dmi13__ren \reg_12_dmi12__ren \reg_11_dmi11__ren \reg_10_dmi10__ren \reg_9_dmi9__ren \reg_8_dmi8__ren \reg_7_dmi7__ren \reg_6_dmi6__ren \reg_5_dmi5__ren \reg_4_dmi4__ren \reg_3_dmi3__ren \reg_2_dmi2__ren \reg_1_dmi1__ren \reg_0_dmi0__ren } \dmi__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $125
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $93
-    connect \B $123
+    connect \A \reg_0_dmi0__data_o
+    connect \B \reg_1_dmi1__data_o
     connect \Y $125
   end
-  process $group_65
-    assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2__data_o $125
-    sync init
-  end
-  process $group_66
-    assign \reg_0_src30__ren 1'0
-    assign \reg_1_src31__ren 1'0
-    assign \reg_2_src32__ren 1'0
-    assign \reg_3_src33__ren 1'0
-    assign \reg_4_src34__ren 1'0
-    assign \reg_5_src35__ren 1'0
-    assign \reg_6_src36__ren 1'0
-    assign \reg_7_src37__ren 1'0
-    assign \reg_8_src38__ren 1'0
-    assign \reg_9_src39__ren 1'0
-    assign \reg_10_src310__ren 1'0
-    assign \reg_11_src311__ren 1'0
-    assign \reg_12_src312__ren 1'0
-    assign \reg_13_src313__ren 1'0
-    assign \reg_14_src314__ren 1'0
-    assign \reg_15_src315__ren 1'0
-    assign \reg_16_src316__ren 1'0
-    assign \reg_17_src317__ren 1'0
-    assign \reg_18_src318__ren 1'0
-    assign \reg_19_src319__ren 1'0
-    assign \reg_20_src320__ren 1'0
-    assign \reg_21_src321__ren 1'0
-    assign \reg_22_src322__ren 1'0
-    assign \reg_23_src323__ren 1'0
-    assign \reg_24_src324__ren 1'0
-    assign \reg_25_src325__ren 1'0
-    assign \reg_26_src326__ren 1'0
-    assign \reg_27_src327__ren 1'0
-    assign \reg_28_src328__ren 1'0
-    assign \reg_29_src329__ren 1'0
-    assign \reg_30_src330__ren 1'0
-    assign \reg_31_src331__ren 1'0
-    assign { \reg_31_src331__ren \reg_30_src330__ren \reg_29_src329__ren \reg_28_src328__ren \reg_27_src327__ren \reg_26_src326__ren \reg_25_src325__ren \reg_24_src324__ren \reg_23_src323__ren \reg_22_src322__ren \reg_21_src321__ren \reg_20_src320__ren \reg_19_src319__ren \reg_18_src318__ren \reg_17_src317__ren \reg_16_src316__ren \reg_15_src315__ren \reg_14_src314__ren \reg_13_src313__ren \reg_12_src312__ren \reg_11_src311__ren \reg_10_src310__ren \reg_9_src39__ren \reg_8_src38__ren \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
-    sync init
-  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $127
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144611,34 +140223,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_0_src30__data_o
-    connect \B \reg_1_src31__data_o
+    connect \A \reg_2_dmi2__data_o
+    connect \B \reg_3_dmi3__data_o
     connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $129
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_2_src32__data_o
-    connect \B \reg_3_src33__data_o
+    connect \A $125
+    connect \B $127
     connect \Y $129
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $131
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $127
-    connect \B $129
+    connect \A \reg_4_dmi4__data_o
+    connect \B \reg_5_dmi5__data_o
     connect \Y $131
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144650,21 +140262,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_4_src34__data_o
-    connect \B \reg_5_src35__data_o
+    connect \A \reg_6_dmi6__data_o
+    connect \B \reg_7_dmi7__data_o
     connect \Y $133
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $135
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_6_src36__data_o
-    connect \B \reg_7_src37__data_o
+    connect \A $131
+    connect \B $133
     connect \Y $135
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144676,21 +140288,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $133
+    connect \A $129
     connect \B $135
     connect \Y $137
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $139
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $131
-    connect \B $137
+    connect \A \reg_8_dmi8__data_o
+    connect \B \reg_9_dmi9__data_o
     connect \Y $139
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144702,34 +140314,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_8_src38__data_o
-    connect \B \reg_9_src39__data_o
+    connect \A \reg_10_dmi10__data_o
+    connect \B \reg_11_dmi11__data_o
     connect \Y $141
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $143
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_10_src310__data_o
-    connect \B \reg_11_src311__data_o
+    connect \A $139
+    connect \B $141
     connect \Y $143
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $145
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $141
-    connect \B $143
+    connect \A \reg_12_dmi12__data_o
+    connect \B \reg_13_dmi13__data_o
     connect \Y $145
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144741,21 +140353,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_12_src312__data_o
-    connect \B \reg_13_src313__data_o
+    connect \A \reg_14_dmi14__data_o
+    connect \B \reg_15_dmi15__data_o
     connect \Y $147
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $149
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_14_src314__data_o
-    connect \B \reg_15_src315__data_o
+    connect \A $145
+    connect \B $147
     connect \Y $149
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144767,7 +140379,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $147
+    connect \A $143
     connect \B $149
     connect \Y $151
   end
@@ -144780,21 +140392,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $145
+    connect \A $137
     connect \B $151
     connect \Y $153
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $155
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $139
-    connect \B $153
+    connect \A \reg_16_dmi16__data_o
+    connect \B \reg_17_dmi17__data_o
     connect \Y $155
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144806,34 +140418,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_16_src316__data_o
-    connect \B \reg_17_src317__data_o
+    connect \A \reg_18_dmi18__data_o
+    connect \B \reg_19_dmi19__data_o
     connect \Y $157
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $159
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_18_src318__data_o
-    connect \B \reg_19_src319__data_o
+    connect \A $155
+    connect \B $157
     connect \Y $159
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $161
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $157
-    connect \B $159
+    connect \A \reg_20_dmi20__data_o
+    connect \B \reg_21_dmi21__data_o
     connect \Y $161
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144845,21 +140457,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_20_src320__data_o
-    connect \B \reg_21_src321__data_o
+    connect \A \reg_22_dmi22__data_o
+    connect \B \reg_23_dmi23__data_o
     connect \Y $163
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $165
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_22_src322__data_o
-    connect \B \reg_23_src323__data_o
+    connect \A $161
+    connect \B $163
     connect \Y $165
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144871,21 +140483,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $163
+    connect \A $159
     connect \B $165
     connect \Y $167
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $169
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $161
-    connect \B $167
+    connect \A \reg_24_dmi24__data_o
+    connect \B \reg_25_dmi25__data_o
     connect \Y $169
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144897,34 +140509,34 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_24_src324__data_o
-    connect \B \reg_25_src325__data_o
+    connect \A \reg_26_dmi26__data_o
+    connect \B \reg_27_dmi27__data_o
     connect \Y $171
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $173
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $174
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_26_src326__data_o
-    connect \B \reg_27_src327__data_o
+    connect \A $169
+    connect \B $171
     connect \Y $173
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   wire width 64 $175
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
   cell $or $176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $171
-    connect \B $173
+    connect \A \reg_28_dmi28__data_o
+    connect \B \reg_29_dmi29__data_o
     connect \Y $175
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
@@ -144936,21 +140548,21 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_28_src328__data_o
-    connect \B \reg_29_src329__data_o
+    connect \A \reg_30_dmi30__data_o
+    connect \B \reg_31_dmi31__data_o
     connect \Y $177
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   wire width 64 $179
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
   cell $or $180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \reg_30_src330__data_o
-    connect \B \reg_31_src331__data_o
+    connect \A $175
+    connect \B $177
     connect \Y $179
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
@@ -144962,7 +140574,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $177
+    connect \A $173
     connect \B $179
     connect \Y $181
   end
@@ -144975,7 +140587,7 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $175
+    connect \A $167
     connect \B $181
     connect \Y $183
   end
@@ -144988,871 +140600,218 @@ module \int
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $169
+    connect \A $153
     connect \B $183
     connect \Y $185
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $187
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $188
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $155
-    connect \B $185
-    connect \Y $187
-  end
   process $group_98
-    assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src3__data_o $187
+    assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi__data_o $185
     sync init
   end
   process $group_99
-    assign \reg_0_dmi0__ren 1'0
-    assign \reg_1_dmi1__ren 1'0
-    assign \reg_2_dmi2__ren 1'0
-    assign \reg_3_dmi3__ren 1'0
-    assign \reg_4_dmi4__ren 1'0
-    assign \reg_5_dmi5__ren 1'0
-    assign \reg_6_dmi6__ren 1'0
-    assign \reg_7_dmi7__ren 1'0
-    assign \reg_8_dmi8__ren 1'0
-    assign \reg_9_dmi9__ren 1'0
-    assign \reg_10_dmi10__ren 1'0
-    assign \reg_11_dmi11__ren 1'0
-    assign \reg_12_dmi12__ren 1'0
-    assign \reg_13_dmi13__ren 1'0
-    assign \reg_14_dmi14__ren 1'0
-    assign \reg_15_dmi15__ren 1'0
-    assign \reg_16_dmi16__ren 1'0
-    assign \reg_17_dmi17__ren 1'0
-    assign \reg_18_dmi18__ren 1'0
-    assign \reg_19_dmi19__ren 1'0
-    assign \reg_20_dmi20__ren 1'0
-    assign \reg_21_dmi21__ren 1'0
-    assign \reg_22_dmi22__ren 1'0
-    assign \reg_23_dmi23__ren 1'0
-    assign \reg_24_dmi24__ren 1'0
-    assign \reg_25_dmi25__ren 1'0
-    assign \reg_26_dmi26__ren 1'0
-    assign \reg_27_dmi27__ren 1'0
-    assign \reg_28_dmi28__ren 1'0
-    assign \reg_29_dmi29__ren 1'0
-    assign \reg_30_dmi30__ren 1'0
-    assign \reg_31_dmi31__ren 1'0
-    assign { \reg_31_dmi31__ren \reg_30_dmi30__ren \reg_29_dmi29__ren \reg_28_dmi28__ren \reg_27_dmi27__ren \reg_26_dmi26__ren \reg_25_dmi25__ren \reg_24_dmi24__ren \reg_23_dmi23__ren \reg_22_dmi22__ren \reg_21_dmi21__ren \reg_20_dmi20__ren \reg_19_dmi19__ren \reg_18_dmi18__ren \reg_17_dmi17__ren \reg_16_dmi16__ren \reg_15_dmi15__ren \reg_14_dmi14__ren \reg_13_dmi13__ren \reg_12_dmi12__ren \reg_11_dmi11__ren \reg_10_dmi10__ren \reg_9_dmi9__ren \reg_8_dmi8__ren \reg_7_dmi7__ren \reg_6_dmi6__ren \reg_5_dmi5__ren \reg_4_dmi4__ren \reg_3_dmi3__ren \reg_2_dmi2__ren \reg_1_dmi1__ren \reg_0_dmi0__ren } \dmi__ren
+    assign \reg_0_dest10__wen 1'0
+    assign \reg_1_dest11__wen 1'0
+    assign \reg_2_dest12__wen 1'0
+    assign \reg_3_dest13__wen 1'0
+    assign \reg_4_dest14__wen 1'0
+    assign \reg_5_dest15__wen 1'0
+    assign \reg_6_dest16__wen 1'0
+    assign \reg_7_dest17__wen 1'0
+    assign \reg_8_dest18__wen 1'0
+    assign \reg_9_dest19__wen 1'0
+    assign \reg_10_dest110__wen 1'0
+    assign \reg_11_dest111__wen 1'0
+    assign \reg_12_dest112__wen 1'0
+    assign \reg_13_dest113__wen 1'0
+    assign \reg_14_dest114__wen 1'0
+    assign \reg_15_dest115__wen 1'0
+    assign \reg_16_dest116__wen 1'0
+    assign \reg_17_dest117__wen 1'0
+    assign \reg_18_dest118__wen 1'0
+    assign \reg_19_dest119__wen 1'0
+    assign \reg_20_dest120__wen 1'0
+    assign \reg_21_dest121__wen 1'0
+    assign \reg_22_dest122__wen 1'0
+    assign \reg_23_dest123__wen 1'0
+    assign \reg_24_dest124__wen 1'0
+    assign \reg_25_dest125__wen 1'0
+    assign \reg_26_dest126__wen 1'0
+    assign \reg_27_dest127__wen 1'0
+    assign \reg_28_dest128__wen 1'0
+    assign \reg_29_dest129__wen 1'0
+    assign \reg_30_dest130__wen 1'0
+    assign \reg_31_dest131__wen 1'0
+    assign { \reg_31_dest131__wen \reg_30_dest130__wen \reg_29_dest129__wen \reg_28_dest128__wen \reg_27_dest127__wen \reg_26_dest126__wen \reg_25_dest125__wen \reg_24_dest124__wen \reg_23_dest123__wen \reg_22_dest122__wen \reg_21_dest121__wen \reg_20_dest120__wen \reg_19_dest119__wen \reg_18_dest118__wen \reg_17_dest117__wen \reg_16_dest116__wen \reg_15_dest115__wen \reg_14_dest114__wen \reg_13_dest113__wen \reg_12_dest112__wen \reg_11_dest111__wen \reg_10_dest110__wen \reg_9_dest19__wen \reg_8_dest18__wen \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $189
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $190
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_0_dmi0__data_o
-    connect \B \reg_1_dmi1__data_o
-    connect \Y $189
+  process $group_131
+    assign \reg_0_dest10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_0_dest10__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $191
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $192
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_2_dmi2__data_o
-    connect \B \reg_3_dmi3__data_o
-    connect \Y $191
+  process $group_132
+    assign \reg_1_dest11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_1_dest11__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $193
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $194
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $189
-    connect \B $191
-    connect \Y $193
+  process $group_133
+    assign \reg_2_dest12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_2_dest12__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $195
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $196
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_4_dmi4__data_o
-    connect \B \reg_5_dmi5__data_o
-    connect \Y $195
+  process $group_134
+    assign \reg_3_dest13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_3_dest13__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $197
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $198
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_6_dmi6__data_o
-    connect \B \reg_7_dmi7__data_o
-    connect \Y $197
+  process $group_135
+    assign \reg_4_dest14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_4_dest14__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $199
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $200
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $195
-    connect \B $197
-    connect \Y $199
+  process $group_136
+    assign \reg_5_dest15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_5_dest15__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $201
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $202
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $193
-    connect \B $199
-    connect \Y $201
+  process $group_137
+    assign \reg_6_dest16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_6_dest16__data_i \data_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $203
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $204
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_8_dmi8__data_o
-    connect \B \reg_9_dmi9__data_o
-    connect \Y $203
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $205
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $206
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_10_dmi10__data_o
-    connect \B \reg_11_dmi11__data_o
-    connect \Y $205
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $207
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $208
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $203
-    connect \B $205
-    connect \Y $207
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $209
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $210
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_12_dmi12__data_o
-    connect \B \reg_13_dmi13__data_o
-    connect \Y $209
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $211
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $212
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_14_dmi14__data_o
-    connect \B \reg_15_dmi15__data_o
-    connect \Y $211
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $213
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $214
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $209
-    connect \B $211
-    connect \Y $213
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $215
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $216
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $207
-    connect \B $213
-    connect \Y $215
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $217
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $218
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $201
-    connect \B $215
-    connect \Y $217
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $219
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $220
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_16_dmi16__data_o
-    connect \B \reg_17_dmi17__data_o
-    connect \Y $219
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $221
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $222
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_18_dmi18__data_o
-    connect \B \reg_19_dmi19__data_o
-    connect \Y $221
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $223
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $224
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $219
-    connect \B $221
-    connect \Y $223
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $225
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $226
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_20_dmi20__data_o
-    connect \B \reg_21_dmi21__data_o
-    connect \Y $225
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $227
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $228
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_22_dmi22__data_o
-    connect \B \reg_23_dmi23__data_o
-    connect \Y $227
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $229
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $230
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $225
-    connect \B $227
-    connect \Y $229
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $231
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $232
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $223
-    connect \B $229
-    connect \Y $231
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $233
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $234
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_24_dmi24__data_o
-    connect \B \reg_25_dmi25__data_o
-    connect \Y $233
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $235
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $236
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_26_dmi26__data_o
-    connect \B \reg_27_dmi27__data_o
-    connect \Y $235
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $237
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $238
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $233
-    connect \B $235
-    connect \Y $237
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $239
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $240
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_28_dmi28__data_o
-    connect \B \reg_29_dmi29__data_o
-    connect \Y $239
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $241
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $242
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_30_dmi30__data_o
-    connect \B \reg_31_dmi31__data_o
-    connect \Y $241
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $243
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $244
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $239
-    connect \B $241
-    connect \Y $243
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $245
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $246
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $237
-    connect \B $243
-    connect \Y $245
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $247
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $248
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $231
-    connect \B $245
-    connect \Y $247
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $249
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $250
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $217
-    connect \B $247
-    connect \Y $249
-  end
-  process $group_131
-    assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \dmi__data_o $249
-    sync init
-  end
-  process $group_132
-    assign \reg_0_dest10__wen 1'0
-    assign \reg_1_dest11__wen 1'0
-    assign \reg_2_dest12__wen 1'0
-    assign \reg_3_dest13__wen 1'0
-    assign \reg_4_dest14__wen 1'0
-    assign \reg_5_dest15__wen 1'0
-    assign \reg_6_dest16__wen 1'0
-    assign \reg_7_dest17__wen 1'0
-    assign \reg_8_dest18__wen 1'0
-    assign \reg_9_dest19__wen 1'0
-    assign \reg_10_dest110__wen 1'0
-    assign \reg_11_dest111__wen 1'0
-    assign \reg_12_dest112__wen 1'0
-    assign \reg_13_dest113__wen 1'0
-    assign \reg_14_dest114__wen 1'0
-    assign \reg_15_dest115__wen 1'0
-    assign \reg_16_dest116__wen 1'0
-    assign \reg_17_dest117__wen 1'0
-    assign \reg_18_dest118__wen 1'0
-    assign \reg_19_dest119__wen 1'0
-    assign \reg_20_dest120__wen 1'0
-    assign \reg_21_dest121__wen 1'0
-    assign \reg_22_dest122__wen 1'0
-    assign \reg_23_dest123__wen 1'0
-    assign \reg_24_dest124__wen 1'0
-    assign \reg_25_dest125__wen 1'0
-    assign \reg_26_dest126__wen 1'0
-    assign \reg_27_dest127__wen 1'0
-    assign \reg_28_dest128__wen 1'0
-    assign \reg_29_dest129__wen 1'0
-    assign \reg_30_dest130__wen 1'0
-    assign \reg_31_dest131__wen 1'0
-    assign { \reg_31_dest131__wen \reg_30_dest130__wen \reg_29_dest129__wen \reg_28_dest128__wen \reg_27_dest127__wen \reg_26_dest126__wen \reg_25_dest125__wen \reg_24_dest124__wen \reg_23_dest123__wen \reg_22_dest122__wen \reg_21_dest121__wen \reg_20_dest120__wen \reg_19_dest119__wen \reg_18_dest118__wen \reg_17_dest117__wen \reg_16_dest116__wen \reg_15_dest115__wen \reg_14_dest114__wen \reg_13_dest113__wen \reg_12_dest112__wen \reg_11_dest111__wen \reg_10_dest110__wen \reg_9_dest19__wen \reg_8_dest18__wen \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen
-    sync init
-  end
-  process $group_164
-    assign \reg_0_dest10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_dest10__data_i \data_i
-    sync init
-  end
-  process $group_165
-    assign \reg_1_dest11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_dest11__data_i \data_i
-    sync init
-  end
-  process $group_166
-    assign \reg_2_dest12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_dest12__data_i \data_i
-    sync init
-  end
-  process $group_167
-    assign \reg_3_dest13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_dest13__data_i \data_i
-    sync init
-  end
-  process $group_168
-    assign \reg_4_dest14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_dest14__data_i \data_i
-    sync init
-  end
-  process $group_169
-    assign \reg_5_dest15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_dest15__data_i \data_i
-    sync init
-  end
-  process $group_170
-    assign \reg_6_dest16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_dest16__data_i \data_i
-    sync init
-  end
-  process $group_171
+  process $group_138
     assign \reg_7_dest17__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_7_dest17__data_i \data_i
     sync init
   end
-  process $group_172
+  process $group_139
     assign \reg_8_dest18__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_8_dest18__data_i \data_i
     sync init
   end
-  process $group_173
+  process $group_140
     assign \reg_9_dest19__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_9_dest19__data_i \data_i
     sync init
   end
-  process $group_174
+  process $group_141
     assign \reg_10_dest110__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_10_dest110__data_i \data_i
     sync init
   end
-  process $group_175
+  process $group_142
     assign \reg_11_dest111__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_11_dest111__data_i \data_i
     sync init
   end
-  process $group_176
+  process $group_143
     assign \reg_12_dest112__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_12_dest112__data_i \data_i
     sync init
   end
-  process $group_177
+  process $group_144
     assign \reg_13_dest113__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_13_dest113__data_i \data_i
     sync init
   end
-  process $group_178
+  process $group_145
     assign \reg_14_dest114__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_14_dest114__data_i \data_i
     sync init
   end
-  process $group_179
+  process $group_146
     assign \reg_15_dest115__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_15_dest115__data_i \data_i
     sync init
   end
-  process $group_180
+  process $group_147
     assign \reg_16_dest116__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_16_dest116__data_i \data_i
     sync init
   end
-  process $group_181
+  process $group_148
     assign \reg_17_dest117__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_17_dest117__data_i \data_i
     sync init
   end
-  process $group_182
+  process $group_149
     assign \reg_18_dest118__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_18_dest118__data_i \data_i
     sync init
   end
-  process $group_183
+  process $group_150
     assign \reg_19_dest119__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_19_dest119__data_i \data_i
     sync init
   end
-  process $group_184
+  process $group_151
     assign \reg_20_dest120__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_20_dest120__data_i \data_i
     sync init
   end
-  process $group_185
+  process $group_152
     assign \reg_21_dest121__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_21_dest121__data_i \data_i
     sync init
   end
-  process $group_186
+  process $group_153
     assign \reg_22_dest122__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_22_dest122__data_i \data_i
     sync init
   end
-  process $group_187
+  process $group_154
     assign \reg_23_dest123__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_23_dest123__data_i \data_i
     sync init
   end
-  process $group_188
+  process $group_155
     assign \reg_24_dest124__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_24_dest124__data_i \data_i
     sync init
   end
-  process $group_189
+  process $group_156
     assign \reg_25_dest125__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_25_dest125__data_i \data_i
     sync init
   end
-  process $group_190
+  process $group_157
     assign \reg_26_dest126__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_26_dest126__data_i \data_i
     sync init
   end
-  process $group_191
+  process $group_158
     assign \reg_27_dest127__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_27_dest127__data_i \data_i
     sync init
   end
-  process $group_192
+  process $group_159
     assign \reg_28_dest128__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_28_dest128__data_i \data_i
     sync init
   end
-  process $group_193
+  process $group_160
     assign \reg_29_dest129__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_29_dest129__data_i \data_i
     sync init
   end
-  process $group_194
+  process $group_161
     assign \reg_30_dest130__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_30_dest130__data_i \data_i
     sync init
   end
-  process $group_195
+  process $group_162
     assign \reg_31_dest131__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_31_dest131__data_i \data_i
     sync init
   end
-  process $group_196
-    assign \reg_0_dest20__wen 1'0
-    assign \reg_1_dest21__wen 1'0
-    assign \reg_2_dest22__wen 1'0
-    assign \reg_3_dest23__wen 1'0
-    assign \reg_4_dest24__wen 1'0
-    assign \reg_5_dest25__wen 1'0
-    assign \reg_6_dest26__wen 1'0
-    assign \reg_7_dest27__wen 1'0
-    assign \reg_8_dest28__wen 1'0
-    assign \reg_9_dest29__wen 1'0
-    assign \reg_10_dest210__wen 1'0
-    assign \reg_11_dest211__wen 1'0
-    assign \reg_12_dest212__wen 1'0
-    assign \reg_13_dest213__wen 1'0
-    assign \reg_14_dest214__wen 1'0
-    assign \reg_15_dest215__wen 1'0
-    assign \reg_16_dest216__wen 1'0
-    assign \reg_17_dest217__wen 1'0
-    assign \reg_18_dest218__wen 1'0
-    assign \reg_19_dest219__wen 1'0
-    assign \reg_20_dest220__wen 1'0
-    assign \reg_21_dest221__wen 1'0
-    assign \reg_22_dest222__wen 1'0
-    assign \reg_23_dest223__wen 1'0
-    assign \reg_24_dest224__wen 1'0
-    assign \reg_25_dest225__wen 1'0
-    assign \reg_26_dest226__wen 1'0
-    assign \reg_27_dest227__wen 1'0
-    assign \reg_28_dest228__wen 1'0
-    assign \reg_29_dest229__wen 1'0
-    assign \reg_30_dest230__wen 1'0
-    assign \reg_31_dest231__wen 1'0
-    assign { \reg_31_dest231__wen \reg_30_dest230__wen \reg_29_dest229__wen \reg_28_dest228__wen \reg_27_dest227__wen \reg_26_dest226__wen \reg_25_dest225__wen \reg_24_dest224__wen \reg_23_dest223__wen \reg_22_dest222__wen \reg_21_dest221__wen \reg_20_dest220__wen \reg_19_dest219__wen \reg_18_dest218__wen \reg_17_dest217__wen \reg_16_dest216__wen \reg_15_dest215__wen \reg_14_dest214__wen \reg_13_dest213__wen \reg_12_dest212__wen \reg_11_dest211__wen \reg_10_dest210__wen \reg_9_dest29__wen \reg_8_dest28__wen \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$1
-    sync init
-  end
-  process $group_228
-    assign \reg_0_dest20__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_dest20__data_i \data_i$2
-    sync init
-  end
-  process $group_229
-    assign \reg_1_dest21__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_dest21__data_i \data_i$2
-    sync init
-  end
-  process $group_230
-    assign \reg_2_dest22__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_dest22__data_i \data_i$2
-    sync init
-  end
-  process $group_231
-    assign \reg_3_dest23__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_dest23__data_i \data_i$2
-    sync init
-  end
-  process $group_232
-    assign \reg_4_dest24__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_dest24__data_i \data_i$2
-    sync init
-  end
-  process $group_233
-    assign \reg_5_dest25__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_dest25__data_i \data_i$2
-    sync init
-  end
-  process $group_234
-    assign \reg_6_dest26__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_dest26__data_i \data_i$2
-    sync init
-  end
-  process $group_235
-    assign \reg_7_dest27__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_dest27__data_i \data_i$2
-    sync init
-  end
-  process $group_236
-    assign \reg_8_dest28__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_8_dest28__data_i \data_i$2
-    sync init
-  end
-  process $group_237
-    assign \reg_9_dest29__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_9_dest29__data_i \data_i$2
-    sync init
-  end
-  process $group_238
-    assign \reg_10_dest210__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_10_dest210__data_i \data_i$2
-    sync init
-  end
-  process $group_239
-    assign \reg_11_dest211__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_11_dest211__data_i \data_i$2
-    sync init
-  end
-  process $group_240
-    assign \reg_12_dest212__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_12_dest212__data_i \data_i$2
-    sync init
-  end
-  process $group_241
-    assign \reg_13_dest213__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_13_dest213__data_i \data_i$2
-    sync init
-  end
-  process $group_242
-    assign \reg_14_dest214__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_14_dest214__data_i \data_i$2
-    sync init
-  end
-  process $group_243
-    assign \reg_15_dest215__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_15_dest215__data_i \data_i$2
-    sync init
-  end
-  process $group_244
-    assign \reg_16_dest216__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_16_dest216__data_i \data_i$2
-    sync init
-  end
-  process $group_245
-    assign \reg_17_dest217__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_17_dest217__data_i \data_i$2
-    sync init
-  end
-  process $group_246
-    assign \reg_18_dest218__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_18_dest218__data_i \data_i$2
-    sync init
-  end
-  process $group_247
-    assign \reg_19_dest219__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_19_dest219__data_i \data_i$2
-    sync init
-  end
-  process $group_248
-    assign \reg_20_dest220__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_20_dest220__data_i \data_i$2
-    sync init
-  end
-  process $group_249
-    assign \reg_21_dest221__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_21_dest221__data_i \data_i$2
-    sync init
-  end
-  process $group_250
-    assign \reg_22_dest222__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_22_dest222__data_i \data_i$2
-    sync init
-  end
-  process $group_251
-    assign \reg_23_dest223__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_23_dest223__data_i \data_i$2
-    sync init
-  end
-  process $group_252
-    assign \reg_24_dest224__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_24_dest224__data_i \data_i$2
-    sync init
-  end
-  process $group_253
-    assign \reg_25_dest225__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_25_dest225__data_i \data_i$2
-    sync init
-  end
-  process $group_254
-    assign \reg_26_dest226__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_26_dest226__data_i \data_i$2
-    sync init
-  end
-  process $group_255
-    assign \reg_27_dest227__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_27_dest227__data_i \data_i$2
-    sync init
-  end
-  process $group_256
-    assign \reg_28_dest228__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_28_dest228__data_i \data_i$2
-    sync init
-  end
-  process $group_257
-    assign \reg_29_dest229__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_29_dest229__data_i \data_i$2
-    sync init
-  end
-  process $group_258
-    assign \reg_30_dest230__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_30_dest230__data_i \data_i$2
-    sync init
-  end
-  process $group_259
-    assign \reg_31_dest231__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_31_dest231__data_i \data_i$2
-    sync init
-  end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
 module \reg_0$125
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src10__ren
@@ -146336,9 +141295,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
 module \reg_1$126
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src11__ren
@@ -146822,9 +141781,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
 module \reg_2$127
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src12__ren
@@ -147308,9 +142267,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
 module \reg_3$128
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src13__ren
@@ -147794,9 +142753,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
 module \reg_4$129
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src14__ren
@@ -148280,9 +143239,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
 module \reg_5$130
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src15__ren
@@ -148766,9 +143725,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
 module \reg_6$131
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src16__ren
@@ -149252,9 +144211,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7"
 module \reg_7$132
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src17__ren
@@ -149738,7 +144697,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr"
 module \cr
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 input 1 \full_rd__ren
@@ -149764,7 +144723,7 @@ module \cr
   wire width 8 input 11 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 4 input 12 \data_i
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 13 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
@@ -150613,9 +145572,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0"
 module \reg_0$133
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src10__ren
@@ -151157,9 +146116,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1"
 module \reg_1$134
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src11__ren
@@ -151701,9 +146660,9 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2"
 module \reg_2$135
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src12__ren
@@ -152245,7 +147204,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer"
 module \xer
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 3 input 1 \src1__ren
@@ -152271,7 +147230,7 @@ module \xer
   wire width 3 input 11 \wen$3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 2 input 12 \data_i$4
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 13 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
@@ -152650,46 +147609,18 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0"
 module \reg_0$136
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia0__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia0__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr0__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr0__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src10__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src10__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src20__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src20__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia0__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia0__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest20__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest20__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest30__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest30__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest40__wen
+  wire width 1 input 2 \src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest40__data_i
+  wire width 64 output 3 \src10__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr10__wen
+  wire width 1 input 4 \dest30__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr10__data_i
+  wire width 64 input 5 \dest30__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -152701,7 +147632,7 @@ module \reg_0$136
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia0__ren
+    connect \A \src10__ren
     connect \B 1'1
     connect \Y $1
   end
@@ -152713,35 +147644,11 @@ module \reg_0$136
       case 1'1
         assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \dest30__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
     end
@@ -152756,7 +147663,7 @@ module \reg_0$136
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia0__ren
+    connect \A \src10__ren
     connect \B 1'1
     connect \Y $3
   end
@@ -152775,104 +147682,90 @@ module \reg_0$136
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
   wire width 64 \reg$next
   process $group_1
-    assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia0__data_o \nia0__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia0__data_o \dest20__data_i
-        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \dest30__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \cia0__data_o \dest30__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia0__data_o \dest40__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia0__data_o \d_wr10__data_i
+            assign \src10__data_o \dest30__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \cia0__data_o \reg
+            assign \src10__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_2
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest30__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest30__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
+module \reg_1$137
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \dest31__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 5 \dest31__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr0__ren
+    connect \A \src11__ren
     connect \B 1'1
-    connect \Y $8
+    connect \Y $1
   end
-  process $group_2
-    assign \wr_detect$7 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest31__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$7 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -152880,127 +147773,117 @@ module \reg_0$136
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr0__ren
+    connect \A \src11__ren
     connect \B 1'1
-    connect \Y $10
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \wr_detect
+    connect \Y $5
   end
-  process $group_3
-    assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
+    switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr0__data_o \nia0__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr0__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr0__data_o \dest30__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr0__data_o \dest40__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest31__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \msr0__data_o \d_wr10__data_i
+            assign \src11__data_o \dest31__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
+        switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \msr0__data_o \reg
+            assign \src11__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_2
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest31__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest31__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
+module \reg_2$138
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src12__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src12__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \dest32__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 5 \dest32__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src10__ren
+    connect \A \src12__ren
     connect \B 1'1
-    connect \Y $15
+    connect \Y $1
   end
-  process $group_4
-    assign \wr_detect$14 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest32__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$14 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -153008,127 +147891,117 @@ module \reg_0$136
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src10__ren
+    connect \A \src12__ren
     connect \B 1'1
-    connect \Y $17
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \wr_detect
+    connect \Y $5
   end
-  process $group_5
-    assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
+    switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \nia0__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest30__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest40__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest32__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src10__data_o \d_wr10__data_i
+            assign \src12__data_o \dest32__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
+        switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src10__data_o \reg
+            assign \src12__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_2
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest32__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest32__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
+module \reg_3$139
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src13__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src13__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \dest33__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 5 \dest33__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src20__ren
+    connect \A \src13__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $1
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest33__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -153136,107 +148009,181 @@ module \reg_0$136
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src20__ren
+    connect \A \src13__ren
     connect \B 1'1
-    connect \Y $24
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A \wr_detect
+    connect \Y $5
   end
-  process $group_7
-    assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia0__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \nia0__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest30__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest30__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest40__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest40__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr10__wen }
+        switch { \dest33__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src20__data_o \d_wr10__data_i
+            assign \src13__data_o \dest33__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src20__data_o \reg
+            assign \src13__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
-  process $group_8
+  process $group_2
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia0__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia0__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest20__wen }
+    switch { \dest33__wen }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
       case 1'1
-        assign \reg$next \dest20__data_i
+        assign \reg$next \dest33__data_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest30__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \reg$next \dest30__data_i
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest40__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest40__data_i
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
+module \reg_4$140
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src14__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src14__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \dest34__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 5 \dest34__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src14__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest34__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src14__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest34__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src14__data_o \dest34__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src14__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
+    sync init
+  end
+  process $group_2
+    assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr10__wen }
+    switch { \dest34__wen }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
       case 1'1
-        assign \reg$next \d_wr10__data_i
+        assign \reg$next \dest34__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \coresync_rst
@@ -153250,48 +148197,228 @@ module \reg_0$136
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
-module \reg_1$137
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.fast"
+module \fast
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia1__ren
+  wire width 5 input 1 \src1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia1__data_o
+  wire width 64 output 2 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr1__ren
+  wire width 5 input 3 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr1__data_o
+  wire width 64 input 4 \data_i
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 5 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_0_src10__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_0_src10__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_0_dest30__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_0_dest30__data_i
+  cell \reg_0$136 \reg_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \src10__ren \reg_0_src10__ren
+    connect \src10__data_o \reg_0_src10__data_o
+    connect \dest30__wen \reg_0_dest30__wen
+    connect \dest30__data_i \reg_0_dest30__data_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_src11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_src11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_dest31__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_dest31__data_i
+  cell \reg_1$137 \reg_1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \src11__ren \reg_1_src11__ren
+    connect \src11__data_o \reg_1_src11__data_o
+    connect \dest31__wen \reg_1_dest31__wen
+    connect \dest31__data_i \reg_1_dest31__data_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_2_src12__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_2_src12__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_2_dest32__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_2_dest32__data_i
+  cell \reg_2$138 \reg_2
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \src12__ren \reg_2_src12__ren
+    connect \src12__data_o \reg_2_src12__data_o
+    connect \dest32__wen \reg_2_dest32__wen
+    connect \dest32__data_i \reg_2_dest32__data_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_3_src13__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_3_src13__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_3_dest33__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_3_dest33__data_i
+  cell \reg_3$139 \reg_3
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \src13__ren \reg_3_src13__ren
+    connect \src13__data_o \reg_3_src13__data_o
+    connect \dest33__wen \reg_3_dest33__wen
+    connect \dest33__data_i \reg_3_dest33__data_i
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src11__ren
+  wire width 1 \reg_4_src14__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src11__data_o
+  wire width 64 \reg_4_src14__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src21__ren
+  wire width 1 \reg_4_dest34__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src21__data_o
+  wire width 64 \reg_4_dest34__data_i
+  cell \reg_4$140 \reg_4
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \src14__ren \reg_4_src14__ren
+    connect \src14__data_o \reg_4_src14__data_o
+    connect \dest34__wen \reg_4_dest34__wen
+    connect \dest34__data_i \reg_4_dest34__data_i
+  end
+  process $group_0
+    assign \reg_0_src10__ren 1'0
+    assign \reg_1_src11__ren 1'0
+    assign \reg_2_src12__ren 1'0
+    assign \reg_3_src13__ren 1'0
+    assign \reg_4_src14__ren 1'0
+    assign { \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_0_src10__data_o
+    connect \B \reg_1_src11__data_o
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_3_src13__data_o
+    connect \B \reg_4_src14__data_o
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_2_src12__data_o
+    connect \B $3
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $1
+    connect \B $5
+    connect \Y $7
+  end
+  process $group_5
+    assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1__data_o $7
+    sync init
+  end
+  process $group_6
+    assign \reg_0_dest30__wen 1'0
+    assign \reg_1_dest31__wen 1'0
+    assign \reg_2_dest32__wen 1'0
+    assign \reg_3_dest33__wen 1'0
+    assign \reg_4_dest34__wen 1'0
+    assign { \reg_4_dest34__wen \reg_3_dest33__wen \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen
+    sync init
+  end
+  process $group_11
+    assign \reg_0_dest30__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_0_dest30__data_i \data_i
+    sync init
+  end
+  process $group_12
+    assign \reg_1_dest31__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_1_dest31__data_i \data_i
+    sync init
+  end
+  process $group_13
+    assign \reg_2_dest32__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_2_dest32__data_i \data_i
+    sync init
+  end
+  process $group_14
+    assign \reg_3_dest33__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_3_dest33__data_i \data_i
+    sync init
+  end
+  process $group_15
+    assign \reg_4_dest34__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_4_dest34__data_i \data_i
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.state.reg_0"
+module \reg_0$141
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia1__wen
+  wire width 1 input 2 \cia0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia1__data_i
+  wire width 64 output 3 \cia0__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest21__wen
+  wire width 1 input 4 \msr0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest21__data_i
+  wire width 64 output 5 \msr0__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest31__wen
+  wire width 1 input 6 \nia0__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest31__data_i
+  wire width 64 input 7 \nia0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest41__wen
+  wire width 1 input 8 \msr0__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest41__data_i
+  wire width 64 input 9 \msr0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr11__wen
+  wire width 1 input 10 \d_wr10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr11__data_i
+  wire width 64 input 11 \d_wr10__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -153303,7 +148430,7 @@ module \reg_1$137
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia1__ren
+    connect \A \cia0__ren
     connect \B 1'1
     connect \Y $1
   end
@@ -153315,31 +148442,19 @@ module \reg_1$137
       case 1'1
         assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia1__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
+        switch { \nia0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr11__wen }
+        switch { \d_wr10__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect 1'1
@@ -153358,7 +148473,7 @@ module \reg_1$137
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia1__ren
+    connect \A \cia0__ren
     connect \B 1'1
     connect \Y $3
   end
@@ -153377,50 +148492,38 @@ module \reg_1$137
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
   wire width 64 \reg$next
   process $group_1
-    assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia1__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia1__data_o \nia1__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia1__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
+        switch { \nia0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \cia1__data_o \dest31__data_i
+            assign \cia0__data_o \nia0__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \cia1__data_o \dest41__data_i
+            assign \cia0__data_o \msr0__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr11__wen }
+        switch { \d_wr10__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \cia1__data_o \d_wr11__data_i
+            assign \cia0__data_o \d_wr10__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \cia1__data_o \reg
+            assign \cia0__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
@@ -153435,7 +148538,7 @@ module \reg_1$137
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr1__ren
+    connect \A \msr0__ren
     connect \B 1'1
     connect \Y $8
   end
@@ -153447,31 +148550,19 @@ module \reg_1$137
       case 1'1
         assign \wr_detect$7 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia1__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
+        switch { \nia0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect$7 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect$7 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr11__wen }
+        switch { \d_wr10__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
             assign \wr_detect$7 1'1
@@ -153490,7 +148581,7 @@ module \reg_1$137
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr1__ren
+    connect \A \msr0__ren
     connect \B 1'1
     connect \Y $10
   end
@@ -153505,104 +148596,138 @@ module \reg_1$137
     connect \Y $12
   end
   process $group_3
-    assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
     switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia1__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr1__data_o \nia1__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr1__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
+        switch { \nia0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \msr1__data_o \dest31__data_i
+            assign \msr0__data_o \nia0__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr0__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \msr1__data_o \dest41__data_i
+            assign \msr0__data_o \msr0__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr11__wen }
+        switch { \d_wr10__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \msr1__data_o \d_wr11__data_i
+            assign \msr0__data_o \d_wr10__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
         switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \msr1__data_o \reg
+            assign \msr0__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_4
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \nia0__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \nia0__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \msr0__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \msr0__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \d_wr10__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \d_wr10__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.state.reg_1"
+module \reg_1$142
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \cia1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \cia1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \msr1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \msr1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \nia1__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 7 \nia1__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \msr1__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 9 \msr1__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \d_wr11__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \d_wr11__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
+  wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src11__ren
+    connect \A \cia1__ren
     connect \B 1'1
-    connect \Y $15
+    connect \Y $1
   end
-  process $group_4
-    assign \wr_detect$14 1'0
+  process $group_0
+    assign \wr_detect 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
+    switch { $1 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$14 1'0
+        assign \wr_detect 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \nia1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
+            assign \wr_detect 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$14 1'1
+            assign \wr_detect 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \d_wr11__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$14 1'1
+            assign \wr_detect 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -153610,127 +148735,107 @@ module \reg_1$137
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src11__ren
+    connect \A \cia1__ren
     connect \B 1'1
-    connect \Y $17
+    connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \wr_detect
+    connect \Y $5
   end
-  process $group_5
-    assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
+    switch { $3 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \nia1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src11__data_o \nia1__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src11__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src11__data_o \dest31__data_i
+            assign \cia1__data_o \nia1__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src11__data_o \dest41__data_i
+            assign \cia1__data_o \msr1__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \d_wr11__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src11__data_o \d_wr11__data_i
+            assign \cia1__data_o \d_wr11__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
+        switch { $5 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src11__data_o \reg
+            assign \cia1__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
+  wire width 1 \wr_detect$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
+  wire width 1 $8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  cell $eq $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
+    connect \A \msr1__ren
     connect \B 1'1
-    connect \Y $22
+    connect \Y $8
   end
-  process $group_6
-    assign \wr_detect$21 1'0
+  process $group_2
+    assign \wr_detect$7 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
+    switch { $8 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
-        assign \wr_detect$21 1'0
+        assign \wr_detect$7 1'0
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \nia1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
+            assign \wr_detect$7 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
+            assign \wr_detect$7 1'1
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \d_wr11__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \wr_detect$21 1'1
+            assign \wr_detect$7 1'1
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
@@ -153738,77 +148843,65 @@ module \reg_1$137
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
+  wire width 1 $10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  cell $eq $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
+    connect \A \msr1__ren
     connect \B 1'1
-    connect \Y $24
+    connect \Y $10
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
+  wire width 1 $12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  cell $not $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A \wr_detect$7
+    connect \Y $12
   end
-  process $group_7
-    assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+  process $group_3
+    assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
+    switch { $10 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \nia1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src21__data_o \nia1__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src21__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest31__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src21__data_o \dest31__data_i
+            assign \msr1__data_o \nia1__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest41__wen }
+        switch { \msr1__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src21__data_o \dest41__data_i
+            assign \msr1__data_o \msr1__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
         switch { \d_wr11__wen }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
           case 1'1
-            assign \src21__data_o \d_wr11__data_i
+            assign \msr1__data_o \d_wr11__data_i
         end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
+        switch { $12 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
           case 1'1
-            assign \src21__data_o \reg
+            assign \msr1__data_o \reg
         end
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
       case
-        assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
-  process $group_8
+  process $group_4
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \nia1__wen }
@@ -153817,22 +148910,10 @@ module \reg_1$137
         assign \reg$next \nia1__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest21__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest21__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest31__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest31__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest41__wen }
+    switch { \msr1__wen }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
       case 1'1
-        assign \reg$next \dest41__data_i
+        assign \reg$next \msr1__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \d_wr11__wen }
@@ -153852,6116 +148933,2353 @@ module \reg_1$137
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
-module \reg_2$138
-  attribute \src "simple/issuer.py:87"
+attribute \nmigen.hierarchy "test_issuer.core.state"
+module \state
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia2__ren
+  wire width 2 input 1 \cia__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 2 \cia__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 input 3 \msr__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 4 \msr__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 input 5 \state_nia_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia2__data_o
+  wire width 2 input 6 \wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 7 \data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr2__ren
+  wire width 64 input 8 \data_i$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr2__data_o
+  wire width 2 input 9 \wen$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src12__ren
+  wire width 64 input 10 \data_i$3
+  attribute \src "simple/issuer.py:89"
+  wire width 1 input 11 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src12__data_o
+  wire width 1 \reg_0_cia0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src22__ren
+  wire width 64 \reg_0_cia0__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src22__data_o
+  wire width 1 \reg_0_msr0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia2__wen
+  wire width 64 \reg_0_msr0__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia2__data_i
+  wire width 1 \reg_0_nia0__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest22__wen
+  wire width 64 \reg_0_nia0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest22__data_i
+  wire width 1 \reg_0_msr0__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest32__wen
+  wire width 64 \reg_0_msr0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest32__data_i
+  wire width 1 \reg_0_d_wr10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest42__wen
+  wire width 64 \reg_0_d_wr10__data_i
+  cell \reg_0$141 \reg_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \cia0__ren \reg_0_cia0__ren
+    connect \cia0__data_o \reg_0_cia0__data_o
+    connect \msr0__ren \reg_0_msr0__ren
+    connect \msr0__data_o \reg_0_msr0__data_o
+    connect \nia0__wen \reg_0_nia0__wen
+    connect \nia0__data_i \reg_0_nia0__data_i
+    connect \msr0__wen \reg_0_msr0__wen
+    connect \msr0__data_i \reg_0_msr0__data_i
+    connect \d_wr10__wen \reg_0_d_wr10__wen
+    connect \d_wr10__data_i \reg_0_d_wr10__data_i
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest42__data_i
+  wire width 1 \reg_1_cia1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr12__wen
+  wire width 64 \reg_1_cia1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr12__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  wire width 1 \reg_1_msr1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_msr1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_nia1__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_nia1__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_msr1__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_msr1__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_d_wr11__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_d_wr11__data_i
+  cell \reg_1$142 \reg_1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \cia1__ren \reg_1_cia1__ren
+    connect \cia1__data_o \reg_1_cia1__data_o
+    connect \msr1__ren \reg_1_msr1__ren
+    connect \msr1__data_o \reg_1_msr1__data_o
+    connect \nia1__wen \reg_1_nia1__wen
+    connect \nia1__data_i \reg_1_nia1__data_i
+    connect \msr1__wen \reg_1_msr1__wen
+    connect \msr1__data_i \reg_1_msr1__data_i
+    connect \d_wr11__wen \reg_1_d_wr11__wen
+    connect \d_wr11__data_i \reg_1_d_wr11__data_i
+  end
+  process $group_0
+    assign \reg_0_cia0__ren 1'0
+    assign \reg_1_cia1__ren 1'0
+    assign { \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cia2__ren
-    connect \B 1'1
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_0_cia0__data_o
+    connect \B \reg_1_cia1__data_o
+    connect \Y $4
+  end
+  process $group_2
+    assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \cia__data_o $4
+    sync init
+  end
+  process $group_3
+    assign \reg_0_msr0__ren 1'0
+    assign \reg_1_msr1__ren 1'0
+    assign { \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_0_msr0__data_o
+    connect \B \reg_1_msr1__data_o
+    connect \Y $6
+  end
+  process $group_5
+    assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \msr__data_o $6
+    sync init
+  end
+  process $group_6
+    assign \reg_0_nia0__wen 1'0
+    assign \reg_1_nia1__wen 1'0
+    assign { \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen
+    sync init
+  end
+  process $group_8
+    assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_0_nia0__data_i \data_i$1
+    sync init
+  end
+  process $group_9
+    assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_1_nia1__data_i \data_i$1
+    sync init
+  end
+  process $group_10
+    assign \reg_0_msr0__wen 1'0
+    assign \reg_1_msr1__wen 1'0
+    assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$2
+    sync init
+  end
+  process $group_12
+    assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_0_msr0__data_i \data_i$3
+    sync init
+  end
+  process $group_13
+    assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_1_msr1__data_i \data_i$3
+    sync init
+  end
+  process $group_14
+    assign \reg_0_d_wr10__wen 1'0
+    assign \reg_1_d_wr11__wen 1'0
+    assign { \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen
+    sync init
+  end
+  process $group_16
+    assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_0_d_wr10__data_i \data_i
+    sync init
+  end
+  process $group_17
+    assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \reg_1_d_wr11__data_i \data_i
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra"
+module \rdpick_INT_ra
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 9 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 9 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 9 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 9 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 9
+    connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \ni 9'000000000
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \cia2__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia2__data_o \nia2__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia2__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia2__data_o \dest32__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia2__data_o \dest42__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia2__data_o \d_wr12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia2__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \msr2__ren
-    connect \B 1'1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
     connect \Y $8
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr2__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
     connect \Y $12
   end
-  process $group_3
-    assign \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr2__data_o \nia2__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr2__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr2__data_o \dest32__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr2__data_o \dest42__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr2__data_o \d_wr12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr2__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src12__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $12
+    connect \Y $11
   end
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $17
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \src12__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $16
+    connect \Y $15
   end
   process $group_5
-    assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \nia2__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest32__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest42__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \d_wr12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src12__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t4 1'0
+    assign \t4 $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+    connect \Y $20
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A $20
+    connect \Y $19
   end
   process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t5 1'0
+    assign \t5 $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
-    connect \B 1'1
+    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A $24
+    connect \Y $23
   end
   process $group_7
-    assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia2__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \nia2__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest32__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest32__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest42__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest42__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \d_wr12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src22__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t6 1'0
+    assign \t6 $23
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $29
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \Y_WIDTH 1
+    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+    connect \Y $28
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $28
+    connect \Y $27
+  end
   process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia2__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia2__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest22__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest22__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest32__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest32__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest42__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest42__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr12__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr12__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t7 1'0
+    assign \t7 $27
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
-module \reg_3$139
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src13__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src13__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia3__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia3__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest23__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest23__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest33__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest33__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest43__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest43__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr13__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr13__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 1
+    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia3__ren
-    connect \B 1'1
+    connect \A $32
+    connect \Y $31
+  end
+  process $group_9
+    assign \t8 1'0
+    assign \t8 $31
+    sync init
+  end
+  process $group_10
+    assign \o 9'000000000
+    assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $36
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $35
+  end
+  process $group_11
+    assign \en_o 1'0
+    assign \en_o $35
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rbc"
+module \rdpick_INT_rbc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 10 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 10 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 10 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 10 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 10
+    parameter \Y_WIDTH 10
+    connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \ni 10'0000000000
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \cia3__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia3__data_o \nia3__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia3__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia3__data_o \dest33__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia3__data_o \dest43__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia3__data_o \d_wr13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia3__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \msr3__ren
-    connect \B 1'1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
     connect \Y $8
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr3__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
     connect \Y $12
   end
-  process $group_3
-    assign \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr3__data_o \nia3__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr3__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr3__data_o \dest33__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr3__data_o \dest43__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr3__data_o \d_wr13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr3__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src13__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $12
+    connect \Y $11
   end
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $17
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \src13__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $16
+    connect \Y $15
   end
   process $group_5
-    assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \nia3__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest33__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest43__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \d_wr13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src13__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t4 1'0
+    assign \t4 $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+    connect \Y $20
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A $20
+    connect \Y $19
   end
   process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t5 1'0
+    assign \t5 $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
-    connect \B 1'1
+    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A $24
+    connect \Y $23
   end
   process $group_7
-    assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia3__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \nia3__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest33__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest33__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest43__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest43__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \d_wr13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src23__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t6 1'0
+    assign \t6 $23
     sync init
   end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia3__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia3__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest23__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest23__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest33__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest33__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest43__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest43__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr13__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr13__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $29
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \Y_WIDTH 1
+    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+    connect \Y $28
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
-module \reg_4$140
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia4__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia4__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr4__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr4__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src14__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src14__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src24__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src24__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia4__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia4__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest24__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest24__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest34__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest34__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest44__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest44__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr14__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr14__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia4__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A $28
+    connect \Y $27
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_8
+    assign \t7 1'0
+    assign \t7 $27
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $33
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 9
     parameter \Y_WIDTH 1
-    connect \A \cia4__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
+    connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $32
+    connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \cia4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia4__data_o \nia4__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia4__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia4__data_o \dest34__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia4__data_o \dest44__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia4__data_o \d_wr14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia4__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_9
+    assign \t8 1'0
+    assign \t8 $31
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $37
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 10
+    parameter \Y_WIDTH 1
+    connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] }
+    connect \Y $36
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr4__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A $36
+    connect \Y $35
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_10
+    assign \t9 1'0
+    assign \t9 $35
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  process $group_11
+    assign \o 10'0000000000
+    assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $40
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 10
     parameter \Y_WIDTH 1
-    connect \A \msr4__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \o
+    connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_12
+    assign \en_o 1'0
+    assign \en_o $39
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so"
+module \rdpick_XER_xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 4 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \i
+    connect \Y $1
+  end
+  process $group_0
+    assign \ni 4'0000
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $4
+    connect \Y $3
   end
-  process $group_3
-    assign \msr4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr4__data_o \nia4__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr4__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr4__data_o \dest34__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr4__data_o \dest44__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr4__data_o \d_wr14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr4__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+    connect \Y $8
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src14__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $8
+    connect \Y $7
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \src14__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $12
+    connect \Y $11
+  end
+  process $group_4
+    assign \t3 1'0
+    assign \t3 $11
+    sync init
   end
   process $group_5
-    assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \nia4__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest34__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest44__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \d_wr14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src14__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A \o
+    connect \Y $15
   end
   process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \en_o 1'0
+    assign \en_o $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca"
+module \rdpick_XER_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 3 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 3 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 3 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 3 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \i
+    connect \Y $1
+  end
+  process $group_0
+    assign \ni 3'000
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
-    connect \B 1'1
-    connect \Y $24
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A $4
+    connect \Y $3
   end
-  process $group_7
-    assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia4__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \nia4__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest34__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest34__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest44__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest44__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \d_wr14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src24__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia4__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia4__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest24__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest24__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest34__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest34__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest44__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest44__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr14__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr14__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+    connect \Y $8
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $8
+    connect \Y $7
+  end
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  process $group_4
+    assign \o 3'000
+    assign \o { \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $11
+  end
+  process $group_5
+    assign \en_o 1'0
+    assign \en_o $11
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5"
-module \reg_5$141
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia5__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia5__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr5__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr5__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src15__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src15__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src25__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src25__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia5__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia5__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest25__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest25__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest35__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest35__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest45__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest45__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr15__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr15__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov"
+module \rdpick_XER_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia5__ren
-    connect \B 1'1
+    connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \ni 1'0
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i
+    sync init
+  end
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cia5__ren
-    connect \B 1'1
+    connect \A \o
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr"
+module \rdpick_CR_full_cr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
+  process $group_0
+    assign \ni 1'0
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
   process $group_1
-    assign \cia5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia5__data_o \nia5__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia5__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia5__data_o \dest35__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia5__data_o \dest45__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia5__data_o \d_wr15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia5__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t0 1'0
+    assign \t0 \i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr5__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \o
+    connect \Y $3
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a"
+module \rdpick_CR_cr_a
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 2 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 2 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \i
+    connect \Y $1
+  end
+  process $group_0
+    assign \ni 2'00
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \msr5__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $4
+    connect \Y $3
+  end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
+    sync init
   end
   process $group_3
-    assign \msr5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr5__data_o \nia5__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr5__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr5__data_o \dest35__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr5__data_o \dest45__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr5__data_o \d_wr15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr5__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \o 2'00
+    assign \o { \t1 \t0 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \src15__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \o
+    connect \Y $7
   end
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \en_o 1'0
+    assign \en_o $7
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b"
+module \rdpick_CR_cr_b
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src15__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_0
+    assign \ni 1'0
+    assign \ni $1
+    sync init
   end
-  process $group_5
-    assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \nia5__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest35__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest45__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \d_wr15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src15__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A \o
+    connect \Y $3
   end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c"
+module \rdpick_CR_cr_c
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
-    connect \B 1'1
-    connect \Y $24
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  process $group_0
+    assign \ni 1'0
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i
+    sync init
+  end
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia5__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \nia5__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest35__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest35__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest45__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest45__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \d_wr15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src25__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \o
+    connect \Y $3
   end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia5__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia5__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest25__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest25__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest35__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest35__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest45__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest45__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr15__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr15__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6"
-module \reg_6$142
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia6__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia6__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr6__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr6__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src16__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src16__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia6__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia6__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest26__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest26__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest36__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest36__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest46__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest46__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr16__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr16__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1"
+module \rdpick_FAST_fast1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 5 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 5 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 5 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 5 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cia6__ren
-    connect \B 1'1
+    parameter \A_WIDTH 5
+    parameter \Y_WIDTH 5
+    connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \ni 5'00000
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \cia6__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \cia6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia6__data_o \nia6__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia6__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia6__data_o \dest36__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia6__data_o \dest46__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia6__data_o \d_wr16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia6__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \msr6__ren
-    connect \B 1'1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
     connect \Y $8
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr6__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
     connect \Y $12
   end
-  process $group_3
-    assign \msr6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr6__data_o \nia6__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr6__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr6__data_o \dest36__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr6__data_o \dest46__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr6__data_o \d_wr16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr6__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src16__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $12
+    connect \Y $11
   end
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $17
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \src16__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $16
+    connect \Y $15
   end
   process $group_5
-    assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \nia6__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest36__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest46__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \d_wr16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src16__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t4 1'0
+    assign \t4 $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  process $group_6
+    assign \o 5'00000
+    assign \o { \t4 \t3 \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $20
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A \o
+    connect \Y $19
   end
-  process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_7
+    assign \en_o 1'0
+    assign \en_o $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1"
+module \rdpick_SPR_spr1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
-    connect \B 1'1
-    connect \Y $24
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  process $group_0
+    assign \ni 1'0
+    assign \ni $1
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i
+    sync init
+  end
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
-  end
-  process $group_7
-    assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia6__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \nia6__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest36__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest36__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest46__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest46__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \d_wr16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src26__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \o
+    connect \Y $3
   end
-  process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia6__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia6__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest26__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest26__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest36__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest36__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest46__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest46__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr16__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr16__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7"
-module \reg_7$143
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 1 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \cia7__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \cia7__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \msr7__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \msr7__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src17__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src17__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \src27__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src27__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \nia7__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \nia7__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 12 \dest27__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \dest27__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 14 \dest37__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \dest37__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 16 \dest47__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \dest47__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 18 \d_wr17__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \d_wr17__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o"
+module \wrpick_INT_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 10 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 10 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 10 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 10 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cia7__ren
-    connect \B 1'1
+    parameter \A_WIDTH 10
+    parameter \Y_WIDTH 10
+    connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \ni 10'0000000000
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \cia7__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \cia7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia7__data_o \nia7__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia7__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia7__data_o \dest37__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia7__data_o \dest47__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \cia7__data_o \d_wr17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \cia7__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \cia7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \msr7__ren
-    connect \B 1'1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
     connect \Y $8
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \msr7__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
     connect \Y $12
   end
-  process $group_3
-    assign \msr7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr7__data_o \nia7__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr7__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr7__data_o \dest37__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr7__data_o \dest47__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \msr7__data_o \d_wr17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \msr7__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \msr7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src17__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $12
+    connect \Y $11
   end
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $17
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \src17__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $16
+    connect \Y $15
   end
   process $group_5
-    assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \nia7__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest37__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest47__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \d_wr17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src17__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t4 1'0
+    assign \t4 $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+    connect \Y $20
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
-    connect \B 1'1
-    connect \Y $22
+    connect \A $20
+    connect \Y $19
   end
   process $group_6
-    assign \wr_detect$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$21 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$21 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \t5 1'0
+    assign \t5 $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $25
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
-    connect \B 1'1
+    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$21
-    connect \Y $26
+    connect \A $24
+    connect \Y $23
   end
   process $group_7
-    assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \nia7__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \nia7__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest37__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest37__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest47__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest47__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \d_wr17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \d_wr17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $26 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src27__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t6 1'0
+    assign \t6 $23
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $29
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \Y_WIDTH 1
+    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+    connect \Y $28
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $28
+    connect \Y $27
+  end
   process $group_8
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \nia7__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \nia7__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest27__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest27__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest37__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest37__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest47__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest47__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \d_wr17__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \d_wr17__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \t7 1'0
+    assign \t7 $27
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 1
+    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $34
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $32
+    connect \Y $31
+  end
+  process $group_9
+    assign \t8 1'0
+    assign \t8 $31
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $37
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 10
+    parameter \Y_WIDTH 1
+    connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] }
+    connect \Y $36
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $38
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $36
+    connect \Y $35
+  end
+  process $group_10
+    assign \t9 1'0
+    assign \t9 $35
+    sync init
+  end
+  process $group_11
+    assign \o 10'0000000000
+    assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $40
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 10
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $39
+  end
+  process $group_12
+    assign \en_o 1'0
+    assign \en_o $39
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fast"
-module \fast
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 1 \cia__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 2 \cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 3 \msr__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 4 \msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 5 \fast_nia_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 6 \wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 7 \data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 8 \src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 9 \src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 10 \src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 11 \src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 12 \wen$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 13 \data_i$2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 14 \wen$3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 15 \data_i$4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 16 \data_i$5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 17 \wen$6
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 18 \data_i$7
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 19 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_cia0__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_cia0__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_msr0__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_msr0__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_src10__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_src10__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_src20__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_src20__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_nia0__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_nia0__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_dest20__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_dest20__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_dest30__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_dest30__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_dest40__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_dest40__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_0_d_wr10__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_0_d_wr10__data_i
-  cell \reg_0$136 \reg_0
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia0__ren \reg_0_cia0__ren
-    connect \cia0__data_o \reg_0_cia0__data_o
-    connect \msr0__ren \reg_0_msr0__ren
-    connect \msr0__data_o \reg_0_msr0__data_o
-    connect \src10__ren \reg_0_src10__ren
-    connect \src10__data_o \reg_0_src10__data_o
-    connect \src20__ren \reg_0_src20__ren
-    connect \src20__data_o \reg_0_src20__data_o
-    connect \nia0__wen \reg_0_nia0__wen
-    connect \nia0__data_i \reg_0_nia0__data_i
-    connect \dest20__wen \reg_0_dest20__wen
-    connect \dest20__data_i \reg_0_dest20__data_i
-    connect \dest30__wen \reg_0_dest30__wen
-    connect \dest30__data_i \reg_0_dest30__data_i
-    connect \dest40__wen \reg_0_dest40__wen
-    connect \dest40__data_i \reg_0_dest40__data_i
-    connect \d_wr10__wen \reg_0_d_wr10__wen
-    connect \d_wr10__data_i \reg_0_d_wr10__data_i
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_cia1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_cia1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_msr1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_msr1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_src11__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_src11__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_src21__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_src21__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_nia1__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_nia1__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_dest21__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_dest21__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_dest31__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_dest31__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_dest41__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_dest41__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_1_d_wr11__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_1_d_wr11__data_i
-  cell \reg_1$137 \reg_1
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia1__ren \reg_1_cia1__ren
-    connect \cia1__data_o \reg_1_cia1__data_o
-    connect \msr1__ren \reg_1_msr1__ren
-    connect \msr1__data_o \reg_1_msr1__data_o
-    connect \src11__ren \reg_1_src11__ren
-    connect \src11__data_o \reg_1_src11__data_o
-    connect \src21__ren \reg_1_src21__ren
-    connect \src21__data_o \reg_1_src21__data_o
-    connect \nia1__wen \reg_1_nia1__wen
-    connect \nia1__data_i \reg_1_nia1__data_i
-    connect \dest21__wen \reg_1_dest21__wen
-    connect \dest21__data_i \reg_1_dest21__data_i
-    connect \dest31__wen \reg_1_dest31__wen
-    connect \dest31__data_i \reg_1_dest31__data_i
-    connect \dest41__wen \reg_1_dest41__wen
-    connect \dest41__data_i \reg_1_dest41__data_i
-    connect \d_wr11__wen \reg_1_d_wr11__wen
-    connect \d_wr11__data_i \reg_1_d_wr11__data_i
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr"
+module \wrpick_CR_full_cr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 1 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_cia2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_cia2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_msr2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_msr2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_src12__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_src12__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_src22__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_src22__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_nia2__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_nia2__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_dest22__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_dest22__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_dest32__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_dest32__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_dest42__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_dest42__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_2_d_wr12__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_2_d_wr12__data_i
-  cell \reg_2$138 \reg_2
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia2__ren \reg_2_cia2__ren
-    connect \cia2__data_o \reg_2_cia2__data_o
-    connect \msr2__ren \reg_2_msr2__ren
-    connect \msr2__data_o \reg_2_msr2__data_o
-    connect \src12__ren \reg_2_src12__ren
-    connect \src12__data_o \reg_2_src12__data_o
-    connect \src22__ren \reg_2_src22__ren
-    connect \src22__data_o \reg_2_src22__data_o
-    connect \nia2__wen \reg_2_nia2__wen
-    connect \nia2__data_i \reg_2_nia2__data_i
-    connect \dest22__wen \reg_2_dest22__wen
-    connect \dest22__data_i \reg_2_dest22__data_i
-    connect \dest32__wen \reg_2_dest32__wen
-    connect \dest32__data_i \reg_2_dest32__data_i
-    connect \dest42__wen \reg_2_dest42__wen
-    connect \dest42__data_i \reg_2_dest42__data_i
-    connect \d_wr12__wen \reg_2_d_wr12__wen
-    connect \d_wr12__data_i \reg_2_d_wr12__data_i
+  process $group_0
+    assign \ni 1'0
+    assign \ni $1
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_cia3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_cia3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_msr3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_msr3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_src13__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_src13__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_src23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_src23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_nia3__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_nia3__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_dest23__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_dest23__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_dest33__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_dest33__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_dest43__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_dest43__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_3_d_wr13__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_3_d_wr13__data_i
-  cell \reg_3$139 \reg_3
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia3__ren \reg_3_cia3__ren
-    connect \cia3__data_o \reg_3_cia3__data_o
-    connect \msr3__ren \reg_3_msr3__ren
-    connect \msr3__data_o \reg_3_msr3__data_o
-    connect \src13__ren \reg_3_src13__ren
-    connect \src13__data_o \reg_3_src13__data_o
-    connect \src23__ren \reg_3_src23__ren
-    connect \src23__data_o \reg_3_src23__data_o
-    connect \nia3__wen \reg_3_nia3__wen
-    connect \nia3__data_i \reg_3_nia3__data_i
-    connect \dest23__wen \reg_3_dest23__wen
-    connect \dest23__data_i \reg_3_dest23__data_i
-    connect \dest33__wen \reg_3_dest33__wen
-    connect \dest33__data_i \reg_3_dest33__data_i
-    connect \dest43__wen \reg_3_dest43__wen
-    connect \dest43__data_i \reg_3_dest43__data_i
-    connect \d_wr13__wen \reg_3_d_wr13__wen
-    connect \d_wr13__data_i \reg_3_d_wr13__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_cia4__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_cia4__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_msr4__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_msr4__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_src14__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_src14__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_src24__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_src24__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_nia4__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_nia4__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_dest24__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_dest24__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_dest34__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_dest34__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_dest44__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_dest44__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_4_d_wr14__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_4_d_wr14__data_i
-  cell \reg_4$140 \reg_4
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia4__ren \reg_4_cia4__ren
-    connect \cia4__data_o \reg_4_cia4__data_o
-    connect \msr4__ren \reg_4_msr4__ren
-    connect \msr4__data_o \reg_4_msr4__data_o
-    connect \src14__ren \reg_4_src14__ren
-    connect \src14__data_o \reg_4_src14__data_o
-    connect \src24__ren \reg_4_src24__ren
-    connect \src24__data_o \reg_4_src24__data_o
-    connect \nia4__wen \reg_4_nia4__wen
-    connect \nia4__data_i \reg_4_nia4__data_i
-    connect \dest24__wen \reg_4_dest24__wen
-    connect \dest24__data_i \reg_4_dest24__data_i
-    connect \dest34__wen \reg_4_dest34__wen
-    connect \dest34__data_i \reg_4_dest34__data_i
-    connect \dest44__wen \reg_4_dest44__wen
-    connect \dest44__data_i \reg_4_dest44__data_i
-    connect \d_wr14__wen \reg_4_d_wr14__wen
-    connect \d_wr14__data_i \reg_4_d_wr14__data_i
+  process $group_2
+    assign \o 1'0
+    assign \o { \t0 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_cia5__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_cia5__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_msr5__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_msr5__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_src15__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_src15__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_src25__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_src25__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_nia5__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_nia5__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_dest25__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_dest25__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_dest35__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_dest35__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_dest45__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_dest45__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_5_d_wr15__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_5_d_wr15__data_i
-  cell \reg_5$141 \reg_5
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia5__ren \reg_5_cia5__ren
-    connect \cia5__data_o \reg_5_cia5__data_o
-    connect \msr5__ren \reg_5_msr5__ren
-    connect \msr5__data_o \reg_5_msr5__data_o
-    connect \src15__ren \reg_5_src15__ren
-    connect \src15__data_o \reg_5_src15__data_o
-    connect \src25__ren \reg_5_src25__ren
-    connect \src25__data_o \reg_5_src25__data_o
-    connect \nia5__wen \reg_5_nia5__wen
-    connect \nia5__data_i \reg_5_nia5__data_i
-    connect \dest25__wen \reg_5_dest25__wen
-    connect \dest25__data_i \reg_5_dest25__data_i
-    connect \dest35__wen \reg_5_dest35__wen
-    connect \dest35__data_i \reg_5_dest35__data_i
-    connect \dest45__wen \reg_5_dest45__wen
-    connect \dest45__data_i \reg_5_dest45__data_i
-    connect \d_wr15__wen \reg_5_d_wr15__wen
-    connect \d_wr15__data_i \reg_5_d_wr15__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_cia6__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_cia6__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_msr6__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_msr6__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_src16__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_src16__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_src26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_src26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_nia6__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_nia6__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_dest26__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_dest26__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_dest36__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_dest36__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_dest46__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_dest46__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_6_d_wr16__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_6_d_wr16__data_i
-  cell \reg_6$142 \reg_6
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia6__ren \reg_6_cia6__ren
-    connect \cia6__data_o \reg_6_cia6__data_o
-    connect \msr6__ren \reg_6_msr6__ren
-    connect \msr6__data_o \reg_6_msr6__data_o
-    connect \src16__ren \reg_6_src16__ren
-    connect \src16__data_o \reg_6_src16__data_o
-    connect \src26__ren \reg_6_src26__ren
-    connect \src26__data_o \reg_6_src26__data_o
-    connect \nia6__wen \reg_6_nia6__wen
-    connect \nia6__data_i \reg_6_nia6__data_i
-    connect \dest26__wen \reg_6_dest26__wen
-    connect \dest26__data_i \reg_6_dest26__data_i
-    connect \dest36__wen \reg_6_dest36__wen
-    connect \dest36__data_i \reg_6_dest36__data_i
-    connect \dest46__wen \reg_6_dest46__wen
-    connect \dest46__data_i \reg_6_dest46__data_i
-    connect \d_wr16__wen \reg_6_d_wr16__wen
-    connect \d_wr16__data_i \reg_6_d_wr16__data_i
+  process $group_3
+    assign \en_o 1'0
+    assign \en_o $3
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_cia7__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_cia7__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_msr7__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_msr7__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_src17__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_src17__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_src27__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_src27__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_nia7__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_nia7__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_dest27__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_dest27__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_dest37__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_dest37__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_dest47__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_dest47__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \reg_7_d_wr17__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \reg_7_d_wr17__data_i
-  cell \reg_7$143 \reg_7
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \cia7__ren \reg_7_cia7__ren
-    connect \cia7__data_o \reg_7_cia7__data_o
-    connect \msr7__ren \reg_7_msr7__ren
-    connect \msr7__data_o \reg_7_msr7__data_o
-    connect \src17__ren \reg_7_src17__ren
-    connect \src17__data_o \reg_7_src17__data_o
-    connect \src27__ren \reg_7_src27__ren
-    connect \src27__data_o \reg_7_src27__data_o
-    connect \nia7__wen \reg_7_nia7__wen
-    connect \nia7__data_i \reg_7_nia7__data_i
-    connect \dest27__wen \reg_7_dest27__wen
-    connect \dest27__data_i \reg_7_dest27__data_i
-    connect \dest37__wen \reg_7_dest37__wen
-    connect \dest37__data_i \reg_7_dest37__data_i
-    connect \dest47__wen \reg_7_dest47__wen
-    connect \dest47__data_i \reg_7_dest47__data_i
-    connect \d_wr17__wen \reg_7_d_wr17__wen
-    connect \d_wr17__data_i \reg_7_d_wr17__data_i
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a"
+module \wrpick_CR_cr_a
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 6 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 6 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 6 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 6 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \i
+    connect \Y $1
   end
   process $group_0
-    assign \reg_0_cia0__ren 1'0
-    assign \reg_1_cia1__ren 1'0
-    assign \reg_2_cia2__ren 1'0
-    assign \reg_3_cia3__ren 1'0
-    assign \reg_4_cia4__ren 1'0
-    assign \reg_5_cia5__ren 1'0
-    assign \reg_6_cia6__ren 1'0
-    assign \reg_7_cia7__ren 1'0
-    assign { \reg_7_cia7__ren \reg_6_cia6__ren \reg_5_cia5__ren \reg_4_cia4__ren \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
+    assign \ni 6'000000
+    assign \ni $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_0_cia0__data_o
-    connect \B \reg_1_cia1__data_o
-    connect \Y $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $10
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_2_cia2__data_o
-    connect \B \reg_3_cia3__data_o
-    connect \Y $10
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $8
-    connect \B $10
-    connect \Y $12
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $14
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $15
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_4_cia4__data_o
-    connect \B \reg_5_cia5__data_o
-    connect \Y $14
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+    connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $16
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $17
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_6_cia6__data_o
-    connect \B \reg_7_cia7__data_o
-    connect \Y $16
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $18
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $19
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $14
-    connect \B $16
-    connect \Y $18
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $20
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $21
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A $12
-    connect \B $18
-    connect \Y $20
-  end
-  process $group_8
-    assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \cia__data_o $20
-    sync init
+    connect \Y $11
   end
-  process $group_9
-    assign \reg_0_msr0__ren 1'0
-    assign \reg_1_msr1__ren 1'0
-    assign \reg_2_msr2__ren 1'0
-    assign \reg_3_msr3__ren 1'0
-    assign \reg_4_msr4__ren 1'0
-    assign \reg_5_msr5__ren 1'0
-    assign \reg_6_msr6__ren 1'0
-    assign \reg_7_msr7__ren 1'0
-    assign { \reg_7_msr7__ren \reg_6_msr6__ren \reg_5_msr5__ren \reg_4_msr4__ren \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
+  process $group_4
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $22
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $17
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_0_msr0__data_o
-    connect \B \reg_1_msr1__data_o
-    connect \Y $22
+    parameter \A_WIDTH 5
+    parameter \Y_WIDTH 1
+    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $24
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $25
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $18
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_2_msr2__data_o
-    connect \B \reg_3_msr3__data_o
-    connect \Y $24
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $16
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $26
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $22
-    connect \B $24
-    connect \Y $26
+  process $group_5
+    assign \t4 1'0
+    assign \t4 $15
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $28
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $29
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $21
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_4_msr4__data_o
-    connect \B \reg_5_msr5__data_o
-    connect \Y $28
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+    connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $30
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $22
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_6_msr6__data_o
-    connect \B \reg_7_msr7__data_o
-    connect \Y $30
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $20
+    connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $33
+  process $group_6
+    assign \t5 1'0
+    assign \t5 $19
+    sync init
+  end
+  process $group_7
+    assign \o 6'000000
+    assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $24
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $28
-    connect \B $30
-    connect \Y $32
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $34
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $35
+  process $group_8
+    assign \en_o 1'0
+    assign \en_o $23
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca"
+module \wrpick_XER_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 4 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $26
-    connect \B $32
-    connect \Y $34
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \i
+    connect \Y $1
   end
-  process $group_17
-    assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \msr__data_o $34
+  process $group_0
+    assign \ni 4'0000
+    assign \ni $1
     sync init
   end
-  process $group_18
-    assign \reg_0_src10__ren 1'0
-    assign \reg_1_src11__ren 1'0
-    assign \reg_2_src12__ren 1'0
-    assign \reg_3_src13__ren 1'0
-    assign \reg_4_src14__ren 1'0
-    assign \reg_5_src15__ren 1'0
-    assign \reg_6_src16__ren 1'0
-    assign \reg_7_src17__ren 1'0
-    assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $36
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $37
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_0_src10__data_o
-    connect \B \reg_1_src11__data_o
-    connect \Y $36
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $38
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $39
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_2_src12__data_o
-    connect \B \reg_3_src13__data_o
-    connect \Y $38
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $4
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $40
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $36
-    connect \B $38
-    connect \Y $40
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $42
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $43
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_4_src14__data_o
-    connect \B \reg_5_src15__data_o
-    connect \Y $42
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+    connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $44
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $45
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_6_src16__data_o
-    connect \B \reg_7_src17__data_o
-    connect \Y $44
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $8
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $46
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $47
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $42
-    connect \B $44
-    connect \Y $46
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $48
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $49
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $40
-    connect \B $46
-    connect \Y $48
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $12
+    connect \Y $11
   end
-  process $group_26
-    assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1__data_o $48
+  process $group_4
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  process $group_27
-    assign \reg_0_src20__ren 1'0
-    assign \reg_1_src21__ren 1'0
-    assign \reg_2_src22__ren 1'0
-    assign \reg_3_src23__ren 1'0
-    assign \reg_4_src24__ren 1'0
-    assign \reg_5_src25__ren 1'0
-    assign \reg_6_src26__ren 1'0
-    assign \reg_7_src27__ren 1'0
-    assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
+  process $group_5
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $50
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $51
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_0_src20__data_o
-    connect \B \reg_1_src21__data_o
-    connect \Y $50
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $52
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $53
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_2_src22__data_o
-    connect \B \reg_3_src23__data_o
-    connect \Y $52
+  process $group_6
+    assign \en_o 1'0
+    assign \en_o $15
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $54
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $55
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov"
+module \wrpick_XER_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+  wire width 4 \ni
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $50
-    connect \B $52
-    connect \Y $54
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $56
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $57
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_4_src24__data_o
-    connect \B \reg_5_src25__data_o
-    connect \Y $56
+  process $group_0
+    assign \ni 4'0000
+    assign \ni $1
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $58
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $59
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \reg_6_src26__data_o
-    connect \B \reg_7_src27__data_o
-    connect \Y $58
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t0
+  process $group_1
+    assign \t0 1'0
+    assign \t0 \i [0]
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $60
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $61
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $5
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $56
-    connect \B $58
-    connect \Y $60
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A { \i [0] \ni [1] }
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $62
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $63
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $54
-    connect \B $60
-    connect \Y $62
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $4
+    connect \Y $3
   end
-  process $group_35
-    assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2__data_o $62
+  process $group_2
+    assign \t1 1'0
+    assign \t1 $3
     sync init
   end
-  process $group_36
-    assign \reg_0_nia0__wen 1'0
-    assign \reg_1_nia1__wen 1'0
-    assign \reg_2_nia2__wen 1'0
-    assign \reg_3_nia3__wen 1'0
-    assign \reg_4_nia4__wen 1'0
-    assign \reg_5_nia5__wen 1'0
-    assign \reg_6_nia6__wen 1'0
-    assign \reg_7_nia7__wen 1'0
-    assign { \reg_7_nia7__wen \reg_6_nia6__wen \reg_5_nia5__wen \reg_4_nia4__wen \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \fast_nia_wen
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+    connect \Y $8
   end
-  process $group_44
-    assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_nia0__data_i \data_i$5
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $8
+    connect \Y $7
   end
-  process $group_45
-    assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_nia1__data_i \data_i$5
+  process $group_3
+    assign \t2 1'0
+    assign \t2 $7
     sync init
   end
-  process $group_46
-    assign \reg_2_nia2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_nia2__data_i \data_i$5
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
   end
-  process $group_47
-    assign \reg_3_nia3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_nia3__data_i \data_i$5
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $12
+    connect \Y $11
   end
-  process $group_48
-    assign \reg_4_nia4__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_nia4__data_i \data_i$5
+  process $group_4
+    assign \t3 1'0
+    assign \t3 $11
     sync init
   end
-  process $group_49
-    assign \reg_5_nia5__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_nia5__data_i \data_i$5
+  process $group_5
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
-  process $group_50
-    assign \reg_6_nia6__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_nia6__data_i \data_i$5
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+  cell $reduce_bool $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \o
+    connect \Y $15
   end
-  process $group_51
-    assign \reg_7_nia7__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_nia7__data_i \data_i$5
+  process $group_6
+    assign \en_o 1'0
+    assign \en_o $15
     sync init
   end
-  process $group_52
-    assign \reg_0_dest20__wen 1'0
-    assign \reg_1_dest21__wen 1'0
-    assign \reg_2_dest22__wen 1'0
-    assign \reg_3_dest23__wen 1'0
-    assign \reg_4_dest24__wen 1'0
-    assign \reg_5_dest25__wen 1'0
-    assign \reg_6_dest26__wen 1'0
-    assign \reg_7_dest27__wen 1'0
-    assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$6
-    sync init
-  end
-  process $group_60
-    assign \reg_0_dest20__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_dest20__data_i \data_i$7
-    sync init
-  end
-  process $group_61
-    assign \reg_1_dest21__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_dest21__data_i \data_i$7
-    sync init
-  end
-  process $group_62
-    assign \reg_2_dest22__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_dest22__data_i \data_i$7
-    sync init
-  end
-  process $group_63
-    assign \reg_3_dest23__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_dest23__data_i \data_i$7
-    sync init
-  end
-  process $group_64
-    assign \reg_4_dest24__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_dest24__data_i \data_i$7
-    sync init
-  end
-  process $group_65
-    assign \reg_5_dest25__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_dest25__data_i \data_i$7
-    sync init
-  end
-  process $group_66
-    assign \reg_6_dest26__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_dest26__data_i \data_i$7
-    sync init
-  end
-  process $group_67
-    assign \reg_7_dest27__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_dest27__data_i \data_i$7
-    sync init
-  end
-  process $group_68
-    assign \reg_0_dest30__wen 1'0
-    assign \reg_1_dest31__wen 1'0
-    assign \reg_2_dest32__wen 1'0
-    assign \reg_3_dest33__wen 1'0
-    assign \reg_4_dest34__wen 1'0
-    assign \reg_5_dest35__wen 1'0
-    assign \reg_6_dest36__wen 1'0
-    assign \reg_7_dest37__wen 1'0
-    assign { \reg_7_dest37__wen \reg_6_dest36__wen \reg_5_dest35__wen \reg_4_dest34__wen \reg_3_dest33__wen \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$1
-    sync init
-  end
-  process $group_76
-    assign \reg_0_dest30__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_dest30__data_i \data_i$2
-    sync init
-  end
-  process $group_77
-    assign \reg_1_dest31__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_dest31__data_i \data_i$2
-    sync init
-  end
-  process $group_78
-    assign \reg_2_dest32__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_dest32__data_i \data_i$2
-    sync init
-  end
-  process $group_79
-    assign \reg_3_dest33__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_dest33__data_i \data_i$2
-    sync init
-  end
-  process $group_80
-    assign \reg_4_dest34__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_dest34__data_i \data_i$2
-    sync init
-  end
-  process $group_81
-    assign \reg_5_dest35__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_dest35__data_i \data_i$2
-    sync init
-  end
-  process $group_82
-    assign \reg_6_dest36__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_dest36__data_i \data_i$2
-    sync init
-  end
-  process $group_83
-    assign \reg_7_dest37__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_dest37__data_i \data_i$2
-    sync init
-  end
-  process $group_84
-    assign \reg_0_dest40__wen 1'0
-    assign \reg_1_dest41__wen 1'0
-    assign \reg_2_dest42__wen 1'0
-    assign \reg_3_dest43__wen 1'0
-    assign \reg_4_dest44__wen 1'0
-    assign \reg_5_dest45__wen 1'0
-    assign \reg_6_dest46__wen 1'0
-    assign \reg_7_dest47__wen 1'0
-    assign { \reg_7_dest47__wen \reg_6_dest46__wen \reg_5_dest45__wen \reg_4_dest44__wen \reg_3_dest43__wen \reg_2_dest42__wen \reg_1_dest41__wen \reg_0_dest40__wen } \wen$3
-    sync init
-  end
-  process $group_92
-    assign \reg_0_dest40__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_dest40__data_i \data_i$4
-    sync init
-  end
-  process $group_93
-    assign \reg_1_dest41__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_dest41__data_i \data_i$4
-    sync init
-  end
-  process $group_94
-    assign \reg_2_dest42__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_dest42__data_i \data_i$4
-    sync init
-  end
-  process $group_95
-    assign \reg_3_dest43__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_dest43__data_i \data_i$4
-    sync init
-  end
-  process $group_96
-    assign \reg_4_dest44__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_dest44__data_i \data_i$4
-    sync init
-  end
-  process $group_97
-    assign \reg_5_dest45__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_dest45__data_i \data_i$4
-    sync init
-  end
-  process $group_98
-    assign \reg_6_dest46__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_dest46__data_i \data_i$4
-    sync init
-  end
-  process $group_99
-    assign \reg_7_dest47__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_dest47__data_i \data_i$4
-    sync init
-  end
-  process $group_100
-    assign \reg_0_d_wr10__wen 1'0
-    assign \reg_1_d_wr11__wen 1'0
-    assign \reg_2_d_wr12__wen 1'0
-    assign \reg_3_d_wr13__wen 1'0
-    assign \reg_4_d_wr14__wen 1'0
-    assign \reg_5_d_wr15__wen 1'0
-    assign \reg_6_d_wr16__wen 1'0
-    assign \reg_7_d_wr17__wen 1'0
-    assign { \reg_7_d_wr17__wen \reg_6_d_wr16__wen \reg_5_d_wr15__wen \reg_4_d_wr14__wen \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen
-    sync init
-  end
-  process $group_108
-    assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_0_d_wr10__data_i \data_i
-    sync init
-  end
-  process $group_109
-    assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_1_d_wr11__data_i \data_i
-    sync init
-  end
-  process $group_110
-    assign \reg_2_d_wr12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_2_d_wr12__data_i \data_i
-    sync init
-  end
-  process $group_111
-    assign \reg_3_d_wr13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_3_d_wr13__data_i \data_i
-    sync init
-  end
-  process $group_112
-    assign \reg_4_d_wr14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_4_d_wr14__data_i \data_i
-    sync init
-  end
-  process $group_113
-    assign \reg_5_d_wr15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_5_d_wr15__data_i \data_i
-    sync init
-  end
-  process $group_114
-    assign \reg_6_d_wr16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_6_d_wr16__data_i \data_i
-    sync init
-  end
-  process $group_115
-    assign \reg_7_d_wr17__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \reg_7_d_wr17__data_i \data_i
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.spr"
-module \spr
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 0 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 1 \src__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 2 \src__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 3 \dest__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 4 \dest__data_i
-  attribute \src "simple/issuer.py:87"
-  wire width 1 input 5 \coresync_rst
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:199"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
-  wire width 1 \addrmatch
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-  cell $and $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dest__wen
-    connect \B \addrmatch
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-    switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-        switch { $1 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 6 \dest__waddr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 6 \src__raddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:204"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:204"
-  cell $eq $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A \dest__waddr
-    connect \B \src__raddr
-    connect \Y $3
-  end
-  process $group_1
-    assign \addrmatch 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-    switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-      case 1'1
-        assign \addrmatch $3
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-  cell $and $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dest__wen
-    connect \B \addrmatch
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$19$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$20$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$21$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$22$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$23$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$24$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$25$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$26$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$27$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$28$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$29$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$30$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$31$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$32$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$33$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$34$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$35$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$36$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$37$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$38$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$39$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$40$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$41$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$42$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$43$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$44$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$45$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$46$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$47$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$48$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$49$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$50$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$51$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$52$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$53$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$54$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$55$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$56$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$57$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$58$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$59$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$60$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$61$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$62$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$63$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$64$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$65$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$66$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$67$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$68$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$69$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$70$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$71$next
-  process $group_2
-    assign \src__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-    switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
-          case 1'1
-            assign \src__data_o \dest__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
-        switch { $7 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
-          case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
-            switch \src__raddr
-              case 6'000000
-                assign \src__data_o \reg
-              case 6'000001
-                assign \src__data_o \reg$9
-              case 6'000010
-                assign \src__data_o \reg$10
-              case 6'000011
-                assign \src__data_o \reg$11
-              case 6'000100
-                assign \src__data_o \reg$12
-              case 6'000101
-                assign \src__data_o \reg$13
-              case 6'000110
-                assign \src__data_o \reg$14
-              case 6'000111
-                assign \src__data_o \reg$15
-              case 6'001000
-                assign \src__data_o \reg$16
-              case 6'001001
-                assign \src__data_o \reg$17
-              case 6'001010
-                assign \src__data_o \reg$18
-              case 6'001011
-                assign \src__data_o \reg$19
-              case 6'001100
-                assign \src__data_o \reg$20
-              case 6'001101
-                assign \src__data_o \reg$21
-              case 6'001110
-                assign \src__data_o \reg$22
-              case 6'001111
-                assign \src__data_o \reg$23
-              case 6'010000
-                assign \src__data_o \reg$24
-              case 6'010001
-                assign \src__data_o \reg$25
-              case 6'010010
-                assign \src__data_o \reg$26
-              case 6'010011
-                assign \src__data_o \reg$27
-              case 6'010100
-                assign \src__data_o \reg$28
-              case 6'010101
-                assign \src__data_o \reg$29
-              case 6'010110
-                assign \src__data_o \reg$30
-              case 6'010111
-                assign \src__data_o \reg$31
-              case 6'011000
-                assign \src__data_o \reg$32
-              case 6'011001
-                assign \src__data_o \reg$33
-              case 6'011010
-                assign \src__data_o \reg$34
-              case 6'011011
-                assign \src__data_o \reg$35
-              case 6'011100
-                assign \src__data_o \reg$36
-              case 6'011101
-                assign \src__data_o \reg$37
-              case 6'011110
-                assign \src__data_o \reg$38
-              case 6'011111
-                assign \src__data_o \reg$39
-              case 6'100000
-                assign \src__data_o \reg$40
-              case 6'100001
-                assign \src__data_o \reg$41
-              case 6'100010
-                assign \src__data_o \reg$42
-              case 6'100011
-                assign \src__data_o \reg$43
-              case 6'100100
-                assign \src__data_o \reg$44
-              case 6'100101
-                assign \src__data_o \reg$45
-              case 6'100110
-                assign \src__data_o \reg$46
-              case 6'100111
-                assign \src__data_o \reg$47
-              case 6'101000
-                assign \src__data_o \reg$48
-              case 6'101001
-                assign \src__data_o \reg$49
-              case 6'101010
-                assign \src__data_o \reg$50
-              case 6'101011
-                assign \src__data_o \reg$51
-              case 6'101100
-                assign \src__data_o \reg$52
-              case 6'101101
-                assign \src__data_o \reg$53
-              case 6'101110
-                assign \src__data_o \reg$54
-              case 6'101111
-                assign \src__data_o \reg$55
-              case 6'110000
-                assign \src__data_o \reg$56
-              case 6'110001
-                assign \src__data_o \reg$57
-              case 6'110010
-                assign \src__data_o \reg$58
-              case 6'110011
-                assign \src__data_o \reg$59
-              case 6'110100
-                assign \src__data_o \reg$60
-              case 6'110101
-                assign \src__data_o \reg$61
-              case 6'110110
-                assign \src__data_o \reg$62
-              case 6'110111
-                assign \src__data_o \reg$63
-              case 6'111000
-                assign \src__data_o \reg$64
-              case 6'111001
-                assign \src__data_o \reg$65
-              case 6'111010
-                assign \src__data_o \reg$66
-              case 6'111011
-                assign \src__data_o \reg$67
-              case 6'111100
-                assign \src__data_o \reg$68
-              case 6'111101
-                assign \src__data_o \reg$69
-              case 6'111110
-                assign \src__data_o \reg$70
-              case 6'------
-                assign \src__data_o \reg$71
-            end
-        end
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$72$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$73$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$74$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$75$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$76$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$77$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$78$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$79$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$80$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$81$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$82$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$83$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$84$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$85$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$86$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$87$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$88$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$89$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$90$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$91$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$92$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$93$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$94$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$95$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$96$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$97$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$98$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$99$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$100$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$101$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$102$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$103$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$104$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$105$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$106$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$107$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$108$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$109$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$110$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$111$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$112$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$113$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$114$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$115$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$116$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
-  wire width 64 \reg$117$next
-  process $group_3
-    assign \reg$next \reg
-    assign \reg$9$next \reg$9
-    assign \reg$10$next \reg$10
-    assign \reg$11$next \reg$11
-    assign \reg$12$next \reg$12
-    assign \reg$13$next \reg$13
-    assign \reg$14$next \reg$14
-    assign \reg$15$next \reg$15
-    assign \reg$16$next \reg$16
-    assign \reg$17$next \reg$17
-    assign \reg$18$next \reg$18
-    assign \reg$19$next \reg$19
-    assign \reg$20$next \reg$20
-    assign \reg$21$next \reg$21
-    assign \reg$22$next \reg$22
-    assign \reg$23$next \reg$23
-    assign \reg$24$next \reg$24
-    assign \reg$25$next \reg$25
-    assign \reg$26$next \reg$26
-    assign \reg$27$next \reg$27
-    assign \reg$28$next \reg$28
-    assign \reg$29$next \reg$29
-    assign \reg$30$next \reg$30
-    assign \reg$31$next \reg$31
-    assign \reg$32$next \reg$32
-    assign \reg$33$next \reg$33
-    assign \reg$34$next \reg$34
-    assign \reg$35$next \reg$35
-    assign \reg$36$next \reg$36
-    assign \reg$37$next \reg$37
-    assign \reg$38$next \reg$38
-    assign \reg$39$next \reg$39
-    assign \reg$40$next \reg$40
-    assign \reg$41$next \reg$41
-    assign \reg$42$next \reg$42
-    assign \reg$43$next \reg$43
-    assign \reg$44$next \reg$44
-    assign \reg$45$next \reg$45
-    assign \reg$46$next \reg$46
-    assign \reg$47$next \reg$47
-    assign \reg$48$next \reg$48
-    assign \reg$49$next \reg$49
-    assign \reg$50$next \reg$50
-    assign \reg$51$next \reg$51
-    assign \reg$52$next \reg$52
-    assign \reg$53$next \reg$53
-    assign \reg$54$next \reg$54
-    assign \reg$55$next \reg$55
-    assign \reg$56$next \reg$56
-    assign \reg$57$next \reg$57
-    assign \reg$58$next \reg$58
-    assign \reg$59$next \reg$59
-    assign \reg$60$next \reg$60
-    assign \reg$61$next \reg$61
-    assign \reg$62$next \reg$62
-    assign \reg$63$next \reg$63
-    assign \reg$64$next \reg$64
-    assign \reg$65$next \reg$65
-    assign \reg$66$next \reg$66
-    assign \reg$67$next \reg$67
-    assign \reg$68$next \reg$68
-    assign \reg$69$next \reg$69
-    assign \reg$70$next \reg$70
-    assign \reg$71$next \reg$71
-    assign \reg$72$next \reg$72
-    assign \reg$73$next \reg$73
-    assign \reg$74$next \reg$74
-    assign \reg$75$next \reg$75
-    assign \reg$76$next \reg$76
-    assign \reg$77$next \reg$77
-    assign \reg$78$next \reg$78
-    assign \reg$79$next \reg$79
-    assign \reg$80$next \reg$80
-    assign \reg$81$next \reg$81
-    assign \reg$82$next \reg$82
-    assign \reg$83$next \reg$83
-    assign \reg$84$next \reg$84
-    assign \reg$85$next \reg$85
-    assign \reg$86$next \reg$86
-    assign \reg$87$next \reg$87
-    assign \reg$88$next \reg$88
-    assign \reg$89$next \reg$89
-    assign \reg$90$next \reg$90
-    assign \reg$91$next \reg$91
-    assign \reg$92$next \reg$92
-    assign \reg$93$next \reg$93
-    assign \reg$94$next \reg$94
-    assign \reg$95$next \reg$95
-    assign \reg$96$next \reg$96
-    assign \reg$97$next \reg$97
-    assign \reg$98$next \reg$98
-    assign \reg$99$next \reg$99
-    assign \reg$100$next \reg$100
-    assign \reg$101$next \reg$101
-    assign \reg$102$next \reg$102
-    assign \reg$103$next \reg$103
-    assign \reg$104$next \reg$104
-    assign \reg$105$next \reg$105
-    assign \reg$106$next \reg$106
-    assign \reg$107$next \reg$107
-    assign \reg$108$next \reg$108
-    assign \reg$109$next \reg$109
-    assign \reg$110$next \reg$110
-    assign \reg$111$next \reg$111
-    assign \reg$112$next \reg$112
-    assign \reg$113$next \reg$113
-    assign \reg$114$next \reg$114
-    assign \reg$115$next \reg$115
-    assign \reg$116$next \reg$116
-    assign \reg$117$next \reg$117
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
-    switch { \dest__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:214"
-        switch \dest__waddr
-          case 6'000000
-            assign \reg$next \dest__data_i
-          case 6'000001
-            assign \reg$9$next \dest__data_i
-          case 6'000010
-            assign \reg$10$next \dest__data_i
-          case 6'000011
-            assign \reg$11$next \dest__data_i
-          case 6'000100
-            assign \reg$12$next \dest__data_i
-          case 6'000101
-            assign \reg$13$next \dest__data_i
-          case 6'000110
-            assign \reg$14$next \dest__data_i
-          case 6'000111
-            assign \reg$15$next \dest__data_i
-          case 6'001000
-            assign \reg$16$next \dest__data_i
-          case 6'001001
-            assign \reg$17$next \dest__data_i
-          case 6'001010
-            assign \reg$18$next \dest__data_i
-          case 6'001011
-            assign \reg$19$next \dest__data_i
-          case 6'001100
-            assign \reg$20$next \dest__data_i
-          case 6'001101
-            assign \reg$21$next \dest__data_i
-          case 6'001110
-            assign \reg$22$next \dest__data_i
-          case 6'001111
-            assign \reg$23$next \dest__data_i
-          case 6'010000
-            assign \reg$24$next \dest__data_i
-          case 6'010001
-            assign \reg$25$next \dest__data_i
-          case 6'010010
-            assign \reg$26$next \dest__data_i
-          case 6'010011
-            assign \reg$27$next \dest__data_i
-          case 6'010100
-            assign \reg$28$next \dest__data_i
-          case 6'010101
-            assign \reg$29$next \dest__data_i
-          case 6'010110
-            assign \reg$30$next \dest__data_i
-          case 6'010111
-            assign \reg$31$next \dest__data_i
-          case 6'011000
-            assign \reg$32$next \dest__data_i
-          case 6'011001
-            assign \reg$33$next \dest__data_i
-          case 6'011010
-            assign \reg$34$next \dest__data_i
-          case 6'011011
-            assign \reg$35$next \dest__data_i
-          case 6'011100
-            assign \reg$36$next \dest__data_i
-          case 6'011101
-            assign \reg$37$next \dest__data_i
-          case 6'011110
-            assign \reg$38$next \dest__data_i
-          case 6'011111
-            assign \reg$39$next \dest__data_i
-          case 6'100000
-            assign \reg$40$next \dest__data_i
-          case 6'100001
-            assign \reg$41$next \dest__data_i
-          case 6'100010
-            assign \reg$42$next \dest__data_i
-          case 6'100011
-            assign \reg$43$next \dest__data_i
-          case 6'100100
-            assign \reg$44$next \dest__data_i
-          case 6'100101
-            assign \reg$45$next \dest__data_i
-          case 6'100110
-            assign \reg$46$next \dest__data_i
-          case 6'100111
-            assign \reg$47$next \dest__data_i
-          case 6'101000
-            assign \reg$48$next \dest__data_i
-          case 6'101001
-            assign \reg$49$next \dest__data_i
-          case 6'101010
-            assign \reg$50$next \dest__data_i
-          case 6'101011
-            assign \reg$51$next \dest__data_i
-          case 6'101100
-            assign \reg$52$next \dest__data_i
-          case 6'101101
-            assign \reg$53$next \dest__data_i
-          case 6'101110
-            assign \reg$54$next \dest__data_i
-          case 6'101111
-            assign \reg$55$next \dest__data_i
-          case 6'110000
-            assign \reg$56$next \dest__data_i
-          case 6'110001
-            assign \reg$57$next \dest__data_i
-          case 6'110010
-            assign \reg$58$next \dest__data_i
-          case 6'110011
-            assign \reg$59$next \dest__data_i
-          case 6'110100
-            assign \reg$60$next \dest__data_i
-          case 6'110101
-            assign \reg$61$next \dest__data_i
-          case 6'110110
-            assign \reg$62$next \dest__data_i
-          case 6'110111
-            assign \reg$63$next \dest__data_i
-          case 6'111000
-            assign \reg$64$next \dest__data_i
-          case 6'111001
-            assign \reg$65$next \dest__data_i
-          case 6'111010
-            assign \reg$66$next \dest__data_i
-          case 6'111011
-            assign \reg$67$next \dest__data_i
-          case 6'111100
-            assign \reg$68$next \dest__data_i
-          case 6'111101
-            assign \reg$69$next \dest__data_i
-          case 6'111110
-            assign \reg$70$next \dest__data_i
-          case 6'------
-            assign \reg$71$next \dest__data_i
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$9$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$10$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$11$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$12$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$13$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$14$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$15$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$16$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$17$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$18$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$19$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$20$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$21$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$22$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$23$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$24$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$25$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$26$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$27$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$28$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$29$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$30$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$31$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$32$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$33$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$34$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$35$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$36$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$37$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$38$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$39$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$40$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$41$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$42$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$43$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$44$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$45$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$46$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$47$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$48$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$49$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$50$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$51$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$52$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$53$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$54$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$55$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$56$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$57$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$58$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$59$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$60$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$61$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$62$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$63$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$64$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$65$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$66$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$67$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$68$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$69$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$70$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$71$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$72$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$73$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$74$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$75$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$76$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$77$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$78$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$79$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$80$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$81$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$82$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$83$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$84$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$85$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$86$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$87$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$88$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$89$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$90$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$91$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$92$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$93$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$94$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$95$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$96$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$97$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$98$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$99$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$100$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$101$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$102$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$103$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$104$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$105$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$106$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$107$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$108$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$109$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$110$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$111$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$112$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$113$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$114$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$115$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$116$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \reg$117$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$9 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$10 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$11 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$12 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$13 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$14 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$15 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$16 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$17 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$18 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$19 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$20 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$21 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$22 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$23 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$24 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$25 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$26 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$27 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$28 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$29 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$30 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$31 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$32 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$33 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$34 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$35 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$36 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$37 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$38 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$39 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$40 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$41 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$42 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$43 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$44 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$45 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$46 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$47 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$48 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$49 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$50 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$51 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$52 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$53 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$54 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$55 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$56 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$57 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$58 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$59 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$60 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$65 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$66 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$67 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$68 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$70 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$71 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$75 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$81 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$82 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$83 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$84 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$85 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$86 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$87 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$88 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$89 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$90 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$91 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$92 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$93 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$94 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$95 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$96 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$97 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$98 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$99 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$100 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$102 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$103 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$104 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$105 64'0000000000000000000000000000000000000000000000000000000000000000
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-      update \reg$114 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$115 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$116 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \reg$117 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \coresync_clk
-      update \reg \reg$next
-      update \reg$9 \reg$9$next
-      update \reg$10 \reg$10$next
-      update \reg$11 \reg$11$next
-      update \reg$12 \reg$12$next
-      update \reg$13 \reg$13$next
-      update \reg$14 \reg$14$next
-      update \reg$15 \reg$15$next
-      update \reg$16 \reg$16$next
-      update \reg$17 \reg$17$next
-      update \reg$18 \reg$18$next
-      update \reg$19 \reg$19$next
-      update \reg$20 \reg$20$next
-      update \reg$21 \reg$21$next
-      update \reg$22 \reg$22$next
-      update \reg$23 \reg$23$next
-      update \reg$24 \reg$24$next
-      update \reg$25 \reg$25$next
-      update \reg$26 \reg$26$next
-      update \reg$27 \reg$27$next
-      update \reg$28 \reg$28$next
-      update \reg$29 \reg$29$next
-      update \reg$30 \reg$30$next
-      update \reg$31 \reg$31$next
-      update \reg$32 \reg$32$next
-      update \reg$33 \reg$33$next
-      update \reg$34 \reg$34$next
-      update \reg$35 \reg$35$next
-      update \reg$36 \reg$36$next
-      update \reg$37 \reg$37$next
-      update \reg$38 \reg$38$next
-      update \reg$39 \reg$39$next
-      update \reg$40 \reg$40$next
-      update \reg$41 \reg$41$next
-      update \reg$42 \reg$42$next
-      update \reg$43 \reg$43$next
-      update \reg$44 \reg$44$next
-      update \reg$45 \reg$45$next
-      update \reg$46 \reg$46$next
-      update \reg$47 \reg$47$next
-      update \reg$48 \reg$48$next
-      update \reg$49 \reg$49$next
-      update \reg$50 \reg$50$next
-      update \reg$51 \reg$51$next
-      update \reg$52 \reg$52$next
-      update \reg$53 \reg$53$next
-      update \reg$54 \reg$54$next
-      update \reg$55 \reg$55$next
-      update \reg$56 \reg$56$next
-      update \reg$57 \reg$57$next
-      update \reg$58 \reg$58$next
-      update \reg$59 \reg$59$next
-      update \reg$60 \reg$60$next
-      update \reg$61 \reg$61$next
-      update \reg$62 \reg$62$next
-      update \reg$63 \reg$63$next
-      update \reg$64 \reg$64$next
-      update \reg$65 \reg$65$next
-      update \reg$66 \reg$66$next
-      update \reg$67 \reg$67$next
-      update \reg$68 \reg$68$next
-      update \reg$69 \reg$69$next
-      update \reg$70 \reg$70$next
-      update \reg$71 \reg$71$next
-      update \reg$72 \reg$72$next
-      update \reg$73 \reg$73$next
-      update \reg$74 \reg$74$next
-      update \reg$75 \reg$75$next
-      update \reg$76 \reg$76$next
-      update \reg$77 \reg$77$next
-      update \reg$78 \reg$78$next
-      update \reg$79 \reg$79$next
-      update \reg$80 \reg$80$next
-      update \reg$81 \reg$81$next
-      update \reg$82 \reg$82$next
-      update \reg$83 \reg$83$next
-      update \reg$84 \reg$84$next
-      update \reg$85 \reg$85$next
-      update \reg$86 \reg$86$next
-      update \reg$87 \reg$87$next
-      update \reg$88 \reg$88$next
-      update \reg$89 \reg$89$next
-      update \reg$90 \reg$90$next
-      update \reg$91 \reg$91$next
-      update \reg$92 \reg$92$next
-      update \reg$93 \reg$93$next
-      update \reg$94 \reg$94$next
-      update \reg$95 \reg$95$next
-      update \reg$96 \reg$96$next
-      update \reg$97 \reg$97$next
-      update \reg$98 \reg$98$next
-      update \reg$99 \reg$99$next
-      update \reg$100 \reg$100$next
-      update \reg$101 \reg$101$next
-      update \reg$102 \reg$102$next
-      update \reg$103 \reg$103$next
-      update \reg$104 \reg$104$next
-      update \reg$105 \reg$105$next
-      update \reg$106 \reg$106$next
-      update \reg$107 \reg$107$next
-      update \reg$108 \reg$108$next
-      update \reg$109 \reg$109$next
-      update \reg$110 \reg$110$next
-      update \reg$111 \reg$111$next
-      update \reg$112 \reg$112$next
-      update \reg$113 \reg$113$next
-      update \reg$114 \reg$114$next
-      update \reg$115 \reg$115$next
-      update \reg$116 \reg$116$next
-      update \reg$117 \reg$117$next
-  end
-  connect \dest__waddr 6'000000
-  connect \src__raddr 6'000000
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra"
-module \rdpick_INT_ra
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so"
+module \wrpick_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 9 input 1 \i
+  wire width 4 input 0 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 9 output 2 \o
+  wire width 4 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 9 \ni
+  wire width 4 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 9 $1
+  wire width 4 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
-    parameter \Y_WIDTH 9
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 9'000000000
+    assign \ni 4'0000
     assign \ni $1
     sync init
   end
@@ -160053,185 +151371,50 @@ module \rdpick_INT_ra
     assign \t3 $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $17
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \Y_WIDTH 1
-    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
-    connect \Y $16
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $16
-    connect \Y $15
-  end
   process $group_5
-    assign \t4 1'0
-    assign \t4 $15
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
-    connect \Y $20
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $20
-    connect \Y $19
-  end
-  process $group_6
-    assign \t5 1'0
-    assign \t5 $19
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t6
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $24
-    connect \Y $23
-  end
-  process $group_7
-    assign \t6 1'0
-    assign \t6 $23
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 1
-    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
-    connect \Y $28
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $28
-    connect \Y $27
-  end
-  process $group_8
-    assign \t7 1'0
-    assign \t7 $27
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
-    parameter \Y_WIDTH 1
-    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
-    connect \Y $32
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $34
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $32
-    connect \Y $31
-  end
-  process $group_9
-    assign \t8 1'0
-    assign \t8 $31
-    sync init
-  end
-  process $group_10
-    assign \o 9'000000000
-    assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $35
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $36
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $35
+    connect \Y $15
   end
-  process $group_11
+  process $group_6
     assign \en_o 1'0
-    assign \en_o $35
+    assign \en_o $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb"
-module \rdpick_INT_rb
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1"
+module \wrpick_FAST_fast1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 input 1 \i
+  wire width 5 input 0 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 output 2 \o
+  wire width 5 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 8 \ni
+  wire width 5 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 8 $1
+  wire width 5 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 8
+    parameter \A_WIDTH 5
+    parameter \Y_WIDTH 5
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 8'00000000
+    assign \ni 5'00000
     assign \ni $1
     sync init
   end
@@ -160350,117 +151533,36 @@ module \rdpick_INT_rb
     assign \t4 $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
-    connect \Y $20
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $20
-    connect \Y $19
-  end
   process $group_6
-    assign \t5 1'0
-    assign \t5 $19
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t6
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $24
-    connect \Y $23
-  end
-  process $group_7
-    assign \t6 1'0
-    assign \t6 $23
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 1
-    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
-    connect \Y $28
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $28
-    connect \Y $27
-  end
-  process $group_8
-    assign \t7 1'0
-    assign \t7 $27
-    sync init
-  end
-  process $group_9
-    assign \o 8'00000000
-    assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    assign \o 5'00000
+    assign \o { \t4 \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $31
+  wire width 1 $19
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $32
+  cell $reduce_bool $20
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $31
+    connect \Y $19
   end
-  process $group_10
+  process $group_7
     assign \en_o 1'0
-    assign \en_o $31
+    assign \en_o $19
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc"
-module \rdpick_INT_rc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia"
+module \wrpick_STATE_nia
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 input 1 \i
+  wire width 2 input 0 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 output 2 \o
+  wire width 2 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
   wire width 2 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
@@ -160534,28 +151636,28 @@ module \rdpick_INT_rc
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so"
-module \rdpick_XER_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr"
+module \wrpick_STATE_msr
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 input 1 \i
+  wire width 1 input 0 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 output 2 \o
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 output 2 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 4 \ni
+  wire width 1 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 4 $1
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 4'0000
+    assign \ni 1'0
     assign \ni $1
     sync init
   end
@@ -160563,304 +151665,7 @@ module \rdpick_XER_xer_so
   wire width 1 \t0
   process $group_1
     assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  process $group_5
-    assign \o 4'0000
-    assign \o { \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $15
-  end
-  process $group_6
-    assign \en_o 1'0
-    assign \en_o $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca"
-module \rdpick_XER_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 3'000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $11
-  end
-  process $group_5
-    assign \en_o 1'0
-    assign \en_o $11
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov"
-module \rdpick_XER_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr"
-module \rdpick_CR_full_cr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
+    assign \t0 \i
     sync init
   end
   process $group_2
@@ -160885,1742 +151690,14 @@ module \rdpick_CR_full_cr
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a"
-module \rdpick_CR_cr_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 2 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 2 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 2'00
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  process $group_3
-    assign \o 2'00
-    assign \o { \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $7
-  end
-  process $group_4
-    assign \en_o 1'0
-    assign \en_o $7
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b"
-module \rdpick_CR_cr_b
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1"
+module \wrpick_SPR_spr1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
+  wire width 1 input 0 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c"
-module \rdpick_CR_cr_c
+  wire width 1 output 1 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1"
-module \rdpick_FAST_fast1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 3'000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $11
-  end
-  process $group_5
-    assign \en_o 1'0
-    assign \en_o $11
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2"
-module \rdpick_FAST_fast2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 2 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 2 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 2'00
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  process $group_3
-    assign \o 2'00
-    assign \o { \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $7
-  end
-  process $group_4
-    assign \en_o 1'0
-    assign \en_o $7
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1"
-module \rdpick_SPR_spr1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o"
-module \wrpick_INT_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 9 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 9 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 9 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 9 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
-    parameter \Y_WIDTH 9
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 9'000000000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $17
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \Y_WIDTH 1
-    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
-    connect \Y $16
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $16
-    connect \Y $15
-  end
-  process $group_5
-    assign \t4 1'0
-    assign \t4 $15
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
-    connect \Y $20
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $20
-    connect \Y $19
-  end
-  process $group_6
-    assign \t5 1'0
-    assign \t5 $19
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t6
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $24
-    connect \Y $23
-  end
-  process $group_7
-    assign \t6 1'0
-    assign \t6 $23
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 1
-    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
-    connect \Y $28
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $28
-    connect \Y $27
-  end
-  process $group_8
-    assign \t7 1'0
-    assign \t7 $27
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
-    parameter \Y_WIDTH 1
-    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
-    connect \Y $32
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $34
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $32
-    connect \Y $31
-  end
-  process $group_9
-    assign \t8 1'0
-    assign \t8 $31
-    sync init
-  end
-  process $group_10
-    assign \o 9'000000000
-    assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $36
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 9
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $35
-  end
-  process $group_11
-    assign \en_o 1'0
-    assign \en_o $35
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o1"
-module \wrpick_INT_o1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr"
-module \wrpick_CR_full_cr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a"
-module \wrpick_CR_cr_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 6 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 6 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 6 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 6 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 6'000000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $17
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \Y_WIDTH 1
-    connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
-    connect \Y $16
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $16
-    connect \Y $15
-  end
-  process $group_5
-    assign \t4 1'0
-    assign \t4 $15
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
-    connect \Y $20
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $20
-    connect \Y $19
-  end
-  process $group_6
-    assign \t5 1'0
-    assign \t5 $19
-    sync init
-  end
-  process $group_7
-    assign \o 6'000000
-    assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $24
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $23
-  end
-  process $group_8
-    assign \en_o 1'0
-    assign \en_o $23
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca"
-module \wrpick_XER_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 4 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 4 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 4'0000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  process $group_5
-    assign \o 4'0000
-    assign \o { \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $15
-  end
-  process $group_6
-    assign \en_o 1'0
-    assign \en_o $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov"
-module \wrpick_XER_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 4 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 4 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 4'0000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  process $group_5
-    assign \o 4'0000
-    assign \o { \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $15
-  end
-  process $group_6
-    assign \en_o 1'0
-    assign \en_o $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so"
-module \wrpick_XER_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 4 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 4 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 4'0000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $12
-    connect \Y $11
-  end
-  process $group_4
-    assign \t3 1'0
-    assign \t3 $11
-    sync init
-  end
-  process $group_5
-    assign \o 4'0000
-    assign \o { \t3 \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $15
-  end
-  process $group_6
-    assign \en_o 1'0
-    assign \en_o $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1"
-module \wrpick_FAST_fast1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 3'000
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $8
-    connect \Y $7
-  end
-  process $group_3
-    assign \t2 1'0
-    assign \t2 $7
-    sync init
-  end
-  process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $11
-  end
-  process $group_5
-    assign \en_o 1'0
-    assign \en_o $11
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast2"
-module \wrpick_FAST_fast2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 2 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 2 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 2'00
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  process $group_3
-    assign \o 2'00
-    assign \o { \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $7
-  end
-  process $group_4
-    assign \en_o 1'0
-    assign \en_o $7
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_nia"
-module \wrpick_FAST_nia
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 2 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 2 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 2'00
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i [0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $reduce_bool $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A { \i [0] \ni [1] }
-    connect \Y $4
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $4
-    connect \Y $3
-  end
-  process $group_2
-    assign \t1 1'0
-    assign \t1 $3
-    sync init
-  end
-  process $group_3
-    assign \o 2'00
-    assign \o { \t1 \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $7
-  end
-  process $group_4
-    assign \en_o 1'0
-    assign \en_o $7
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_msr"
-module \wrpick_FAST_msr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 1 \ni
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \Y $1
-  end
-  process $group_0
-    assign \ni 1'0
-    assign \ni $1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
-  wire width 1 \t0
-  process $group_1
-    assign \t0 1'0
-    assign \t0 \i
-    sync init
-  end
-  process $group_2
-    assign \o 1'0
-    assign \o { \t0 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \o
-    connect \Y $3
-  end
-  process $group_3
-    assign \en_o 1'0
-    assign \en_o $3
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1"
-module \wrpick_SPR_spr1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 output 0 \en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 input 1 \i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 output 2 \o
+  wire width 1 output 2 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
   wire width 1 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
@@ -162669,44 +151746,44 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core"
 module \core
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 input 0 \coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82"
   wire width 1 output 1 \corebusy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 2 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 3 \cu_ad__go_i
+  wire width 1 output 3 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 4 \cu_ad__rel_o
+  wire width 1 input 4 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 5 \cu_st__go_i
+  wire width 1 output 5 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 6 \cu_st__rel_o
+  wire width 1 input 6 \cu_st__go_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 7 \cia__ren
+  wire width 2 input 7 \cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 8 \cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90"
   wire width 1 input 9 \core_reset_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91"
   wire width 1 output 10 \core_terminate_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91"
   wire width 1 \core_terminate_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
-  wire width 1 input 11 \valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
-  wire width 1 input 12 \issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
-  wire width 32 input 13 \raw_opcode_in
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 14 \msr__ren
+  wire width 2 input 11 \msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 15 \msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
-  wire width 64 input 16 \dec2_msr
+  wire width 64 output 12 \msr__data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
+  wire width 1 input 13 \valid
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:81"
+  wire width 1 input 14 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
+  wire width 32 input 15 \raw_opcode_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
-  wire width 64 input 17 \dec2_pc
+  wire width 64 input 16 \dec2_pc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 input 17 \dec2_msr
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -162783,9 +151860,9 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
   wire width 7 output 18 \insn_type
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 output 19 \fast_nia_wen
+  wire width 2 output 19 \state_nia_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 20 \wen
+  wire width 2 input 20 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 input 21 \data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -162801,16 +151878,16 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 27 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 28 \dbus__dat_r
+  wire width 8 output 28 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 29 \dbus__adr
+  wire width 64 input 29 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 30 \dbus__sel
+  wire width 45 output 30 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 31 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 64 output 32 \dbus__dat_w
-  attribute \src "simple/issuer.py:87"
+  attribute \src "simple/issuer.py:89"
   wire width 1 \coresync_rst
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -163166,8 +152243,8 @@ module \core
   cell \pdecode2 \pdecode2
     connect \bigendian \bigendian
     connect \raw_opcode_in \raw_opcode_in
-    connect \dec2_msr \dec2_msr
     connect \dec2_pc \dec2_pc
+    connect \dec2_msr \dec2_msr
     connect \insn_type \insn_type
     connect \fn_unit \pdecode2_fn_unit
     connect \imm \pdecode2_imm
@@ -164663,16 +153740,16 @@ module \core
   wire width 1 \fus_fast1_ok$140
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast1_ok$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$144
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast2_ok$145
+  wire width 1 \fus_fast2_ok$142
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest2_o$144
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest3_o$145
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 \fus_dest2_o$146
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
@@ -164717,10 +153794,10 @@ module \core
   wire width 1 \fus_ldst_port0_st_data_i_ok
   cell \fus \fus
     connect \coresync_clk \coresync_clk
+    connect \cu_st__rel_o \cu_st__rel_o
     connect \cu_ad__go_i \cu_ad__go_i
     connect \cu_ad__rel_o \cu_ad__rel_o
     connect \cu_st__go_i \cu_st__go_i
-    connect \cu_st__rel_o \cu_st__rel_o
     connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type
     connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit
     connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm
@@ -165011,11 +154088,11 @@ module \core
     connect \cu_wr__go_i$137 \fus_cu_wr__go_i$139
     connect \fast1_ok$138 \fus_fast1_ok$140
     connect \fast1_ok$139 \fus_fast1_ok$141
-    connect \dest1_o$140 \fus_dest1_o$142
-    connect \dest2_o$141 \fus_dest2_o$143
-    connect \dest3_o$142 \fus_dest3_o$144
     connect \fast2_ok \fus_fast2_ok
-    connect \fast2_ok$143 \fus_fast2_ok$145
+    connect \fast2_ok$140 \fus_fast2_ok$142
+    connect \dest1_o$141 \fus_dest1_o$143
+    connect \dest2_o$142 \fus_dest2_o$144
+    connect \dest3_o$143 \fus_dest3_o$145
     connect \dest2_o$144 \fus_dest2_o$146
     connect \dest3_o$145 \fus_dest3_o$147
     connect \nia_ok \fus_nia_ok
@@ -165039,1438 +154116,3754 @@ module \core
     connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
   end
-  cell \l0 \l0
-    connect \coresync_clk \coresync_clk
-    connect \coresync_rst \coresync_rst
-    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
-    connect \ldst_port0_data_len \fus_ldst_port0_data_len
-    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
-    connect \dbus__cyc \dbus__cyc
-    connect \dbus__ack \dbus__ack
-    connect \dbus__err \dbus__err
-    connect \dbus__stb \dbus__stb
-    connect \dbus__dat_r \dbus__dat_r
-    connect \dbus__adr \dbus__adr
-    connect \dbus__sel \dbus__sel
-    connect \dbus__we \dbus__we
-    connect \dbus__dat_w \dbus__dat_w
+  cell \l0 \l0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \fus_ldst_port0_data_len
+    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
+    connect \dbus__cyc \dbus__cyc
+    connect \dbus__ack \dbus__ack
+    connect \dbus__err \dbus__err
+    connect \dbus__stb \dbus__stb
+    connect \dbus__sel \dbus__sel
+    connect \dbus__dat_r \dbus__dat_r
+    connect \dbus__adr \dbus__adr
+    connect \dbus__we \dbus__we
+    connect \dbus__dat_w \dbus__dat_w
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_data_i
+  cell \int \int
+    connect \coresync_clk \coresync_clk
+    connect \dmi__ren \dmi__ren
+    connect \dmi__data_o \dmi__data_o
+    connect \src1__ren \int_src1__ren
+    connect \src1__data_o \int_src1__data_o
+    connect \src3__ren \int_src3__ren
+    connect \src3__data_o \int_src3__data_o
+    connect \wen \int_wen
+    connect \data_i \int_data_i
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_full_rd__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \cr_full_rd__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_full_wr__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \cr_full_wr__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_data_i
+  cell \cr \cr
+    connect \coresync_clk \coresync_clk
+    connect \full_rd__ren \cr_full_rd__ren
+    connect \full_rd__data_o \cr_full_rd__data_o
+    connect \src1__ren \cr_src1__ren
+    connect \src1__data_o \cr_src1__data_o
+    connect \src2__ren \cr_src2__ren
+    connect \src2__data_o \cr_src2__data_o
+    connect \src3__ren \cr_src3__ren
+    connect \src3__data_o \cr_src3__data_o
+    connect \full_wr__wen \cr_full_wr__wen
+    connect \full_wr__data_i \cr_full_wr__data_i
+    connect \wen \cr_wen
+    connect \data_i \cr_data_i
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen$153
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i$154
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen$155
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i$156
+  cell \xer \xer
+    connect \coresync_clk \coresync_clk
+    connect \src1__ren \xer_src1__ren
+    connect \src1__data_o \xer_src1__data_o
+    connect \src2__ren \xer_src2__ren
+    connect \src2__data_o \xer_src2__data_o
+    connect \src3__ren \xer_src3__ren
+    connect \src3__data_o \xer_src3__data_o
+    connect \wen \xer_wen
+    connect \data_i \xer_data_i
+    connect \wen$1 \xer_wen$153
+    connect \data_i$2 \xer_data_i$154
+    connect \wen$3 \xer_wen$155
+    connect \data_i$4 \xer_data_i$156
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 5 \fast_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 5 \fast_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_data_i
+  cell \fast \fast
+    connect \coresync_clk \coresync_clk
+    connect \src1__ren \fast_src1__ren
+    connect \src1__data_o \fast_src1__data_o
+    connect \wen \fast_wen
+    connect \data_i \fast_data_i
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \state_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \state_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \state_data_i$157
+  cell \state \state
+    connect \coresync_clk \coresync_clk
+    connect \cia__ren \cia__ren
+    connect \cia__data_o \cia__data_o
+    connect \msr__ren \msr__ren
+    connect \msr__data_o \msr__data_o
+    connect \state_nia_wen \state_nia_wen
+    connect \wen \wen
+    connect \data_i \data_i
+    connect \data_i$1 \state_data_i
+    connect \wen$2 \state_wen
+    connect \data_i$3 \state_data_i$157
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 9 \rdpick_INT_ra_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 9 \rdpick_INT_ra_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_INT_ra_en_o
+  cell \rdpick_INT_ra \rdpick_INT_ra
+    connect \i \rdpick_INT_ra_i
+    connect \o \rdpick_INT_ra_o
+    connect \en_o \rdpick_INT_ra_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 10 \rdpick_INT_rbc_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 10 \rdpick_INT_rbc_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_INT_rbc_en_o
+  cell \rdpick_INT_rbc \rdpick_INT_rbc
+    connect \i \rdpick_INT_rbc_i
+    connect \o \rdpick_INT_rbc_o
+    connect \en_o \rdpick_INT_rbc_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \rdpick_XER_xer_so_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \rdpick_XER_xer_so_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_so_en_o
+  cell \rdpick_XER_xer_so \rdpick_XER_xer_so
+    connect \i \rdpick_XER_xer_so_i
+    connect \o \rdpick_XER_xer_so_o
+    connect \en_o \rdpick_XER_xer_so_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 3 \rdpick_XER_xer_ca_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 3 \rdpick_XER_xer_ca_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_ca_en_o
+  cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
+    connect \i \rdpick_XER_xer_ca_i
+    connect \o \rdpick_XER_xer_ca_o
+    connect \en_o \rdpick_XER_xer_ca_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_XER_xer_ov_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_XER_xer_ov_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_ov_en_o
+  cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov
+    connect \i \rdpick_XER_xer_ov_i
+    connect \o \rdpick_XER_xer_ov_o
+    connect \en_o \rdpick_XER_xer_ov_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_full_cr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_full_cr_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_full_cr_en_o
+  cell \rdpick_CR_full_cr \rdpick_CR_full_cr
+    connect \i \rdpick_CR_full_cr_i
+    connect \o \rdpick_CR_full_cr_o
+    connect \en_o \rdpick_CR_full_cr_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \rdpick_CR_cr_a_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \rdpick_CR_cr_a_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_a_en_o
+  cell \rdpick_CR_cr_a \rdpick_CR_cr_a
+    connect \i \rdpick_CR_cr_a_i
+    connect \o \rdpick_CR_cr_a_o
+    connect \en_o \rdpick_CR_cr_a_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_cr_b_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_cr_b_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_b_en_o
+  cell \rdpick_CR_cr_b \rdpick_CR_cr_b
+    connect \i \rdpick_CR_cr_b_i
+    connect \o \rdpick_CR_cr_b_o
+    connect \en_o \rdpick_CR_cr_b_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_cr_c_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_cr_c_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_c_en_o
+  cell \rdpick_CR_cr_c \rdpick_CR_cr_c
+    connect \i \rdpick_CR_cr_c_i
+    connect \o \rdpick_CR_cr_c_o
+    connect \en_o \rdpick_CR_cr_c_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 5 \rdpick_FAST_fast1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 5 \rdpick_FAST_fast1_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_FAST_fast1_en_o
+  cell \rdpick_FAST_fast1 \rdpick_FAST_fast1
+    connect \i \rdpick_FAST_fast1_i
+    connect \o \rdpick_FAST_fast1_o
+    connect \en_o \rdpick_FAST_fast1_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_SPR_spr1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_SPR_spr1_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_SPR_spr1_en_o
+  cell \rdpick_SPR_spr1 \rdpick_SPR_spr1
+    connect \i \rdpick_SPR_spr1_i
+    connect \o \rdpick_SPR_spr1_o
+    connect \en_o \rdpick_SPR_spr1_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 10 \wrpick_INT_o_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 10 \wrpick_INT_o_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_INT_o_en_o
+  cell \wrpick_INT_o \wrpick_INT_o
+    connect \i \wrpick_INT_o_i
+    connect \o \wrpick_INT_o_o
+    connect \en_o \wrpick_INT_o_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_CR_full_cr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_CR_full_cr_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_CR_full_cr_en_o
+  cell \wrpick_CR_full_cr \wrpick_CR_full_cr
+    connect \i \wrpick_CR_full_cr_i
+    connect \o \wrpick_CR_full_cr_o
+    connect \en_o \wrpick_CR_full_cr_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 6 \wrpick_CR_cr_a_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 6 \wrpick_CR_cr_a_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_CR_cr_a_en_o
+  cell \wrpick_CR_cr_a \wrpick_CR_cr_a
+    connect \i \wrpick_CR_cr_a_i
+    connect \o \wrpick_CR_cr_a_o
+    connect \en_o \wrpick_CR_cr_a_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_ca_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_ca_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_ca_en_o
+  cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
+    connect \i \wrpick_XER_xer_ca_i
+    connect \o \wrpick_XER_xer_ca_o
+    connect \en_o \wrpick_XER_xer_ca_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_ov_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_ov_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_ov_en_o
+  cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
+    connect \i \wrpick_XER_xer_ov_i
+    connect \o \wrpick_XER_xer_ov_o
+    connect \en_o \wrpick_XER_xer_ov_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_so_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_so_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_so_en_o
+  cell \wrpick_XER_xer_so \wrpick_XER_xer_so
+    connect \i \wrpick_XER_xer_so_i
+    connect \o \wrpick_XER_xer_so_o
+    connect \en_o \wrpick_XER_xer_so_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 5 \wrpick_FAST_fast1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 5 \wrpick_FAST_fast1_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_FAST_fast1_en_o
+  cell \wrpick_FAST_fast1 \wrpick_FAST_fast1
+    connect \i \wrpick_FAST_fast1_i
+    connect \o \wrpick_FAST_fast1_o
+    connect \en_o \wrpick_FAST_fast1_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \wrpick_STATE_nia_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \wrpick_STATE_nia_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_STATE_nia_en_o
+  cell \wrpick_STATE_nia \wrpick_STATE_nia
+    connect \i \wrpick_STATE_nia_i
+    connect \o \wrpick_STATE_nia_o
+    connect \en_o \wrpick_STATE_nia_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_STATE_msr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_STATE_msr_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_STATE_msr_en_o
+  cell \wrpick_STATE_msr \wrpick_STATE_msr
+    connect \i \wrpick_STATE_msr_i
+    connect \o \wrpick_STATE_msr_o
+    connect \en_o \wrpick_STATE_msr_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_SPR_spr1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_SPR_spr1_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_SPR_spr1_en_o
+  cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
+    connect \i \wrpick_SPR_spr1_i
+    connect \o \wrpick_SPR_spr1_o
+    connect \en_o \wrpick_SPR_spr1_en_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_alu0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $158
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $159
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $160
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 2'10
+    connect \Y $159
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $161
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $159
+    connect \Y $158
+  end
+  process $group_0
+    assign \en_alu0 1'0
+    assign \en_alu0 $158
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:130"
+  wire width 10 \fu_enable
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_branch0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_trap0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_logical0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_spr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_div0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_mul0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_shiftrot0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+  wire width 1 \en_ldst0
+  process $group_1
+    assign \fu_enable 10'0000000000
+    assign \fu_enable [0] \en_alu0
+    assign \fu_enable [1] \en_cr0
+    assign \fu_enable [2] \en_branch0
+    assign \fu_enable [3] \en_trap0
+    assign \fu_enable [4] \en_logical0
+    assign \fu_enable [5] \en_spr0
+    assign \fu_enable [6] \en_div0
+    assign \fu_enable [7] \en_mul0
+    assign \fu_enable [8] \en_shiftrot0
+    assign \fu_enable [9] \en_ldst0
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $162
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $163
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $164
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 7'1000000
+    connect \Y $163
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $165
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $163
+    connect \Y $162
+  end
+  process $group_2
+    assign \en_cr0 1'0
+    assign \en_cr0 $162
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $166
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $167
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $168
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 6'100000
+    connect \Y $167
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $169
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $167
+    connect \Y $166
+  end
+  process $group_3
+    assign \en_branch0 1'0
+    assign \en_branch0 $166
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $170
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $171
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $172
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 8'10000000
+    connect \Y $171
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $173
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $171
+    connect \Y $170
+  end
+  process $group_4
+    assign \en_trap0 1'0
+    assign \en_trap0 $170
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $174
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $175
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $176
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 5'10000
+    connect \Y $175
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $177
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $175
+    connect \Y $174
+  end
+  process $group_5
+    assign \en_logical0 1'0
+    assign \en_logical0 $174
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $178
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $179
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $180
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 11
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 11'10000000000
+    connect \Y $179
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $181
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $179
+    connect \Y $178
+  end
+  process $group_6
+    assign \en_spr0 1'0
+    assign \en_spr0 $178
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $182
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $183
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $184
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 10
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 10'1000000000
+    connect \Y $183
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $185
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $183
+    connect \Y $182
+  end
+  process $group_7
+    assign \en_div0 1'0
+    assign \en_div0 $182
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $186
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $187
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $188
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 9
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 9'100000000
+    connect \Y $187
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $189
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $187
+    connect \Y $186
+  end
+  process $group_8
+    assign \en_mul0 1'0
+    assign \en_mul0 $186
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $190
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $191
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $192
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 4'1000
+    connect \Y $191
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $193
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $191
+    connect \Y $190
+  end
+  process $group_9
+    assign \en_shiftrot0 1'0
+    assign \en_shiftrot0 $190
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $194
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 11 $195
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $196
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 3'100
+    connect \Y $195
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $reduce_bool $197
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $195
+    connect \Y $194
+  end
+  process $group_10
+    assign \en_ldst0 1'0
+    assign \en_ldst0 $194
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
+  wire width 2 \counter
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
+  wire width 2 \counter$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+  wire width 1 $198
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+  cell $ne $199
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \counter
+    connect \B 1'0
+    connect \Y $198
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  wire width 3 $200
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  wire width 3 $201
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  cell $sub $202
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \counter
+    connect \B 1'1
+    connect \Y $201
+  end
+  connect $200 $201
+  process $group_11
+    assign \counter$next \counter
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+    switch { $198 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+      case 1'1
+        assign \counter$next $200 [1:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+            assign \counter$next 2'10
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \counter$next 2'00
+    end
+    sync init
+      update \counter 2'00
+    sync posedge \coresync_clk
+      update \counter \counter$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+  wire width 1 $203
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+  cell $ne $204
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \counter
+    connect \B 1'0
+    connect \Y $203
+  end
+  process $group_12
+    assign \corebusy_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+    switch { $203 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146"
+      case 1'1
+        assign \corebusy_o 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+            assign \corebusy_o 1'1
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$4
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$7
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$10
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$13
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$16
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$19
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$22
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$25
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$28
+            end
+        end
+    end
+    sync init
+  end
+  process $group_13
+    assign \core_terminate_o$next \core_terminate_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+            assign \core_terminate_o$next 1'1
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \core_terminate_o$next 1'0
+    end
+    sync init
+      update \core_terminate_o 1'0
+    sync posedge \coresync_clk
+      update \core_terminate_o \core_terminate_o$next
+  end
+  process $group_14
+    assign \fus_oper_i_alu_alu0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_15
+    assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_16
+    assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_18
+    assign \fus_oper_i_alu_alu0__rc__rc 1'0
+    assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_20
+    assign \fus_oper_i_alu_alu0__oe__oe 1'0
+    assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_22
+    assign \fus_oper_i_alu_alu0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
+  end
+  process $group_23
+    assign \fus_oper_i_alu_alu0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
+  end
+  process $group_24
+    assign \fus_oper_i_alu_alu0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out
+            end
+        end
+    end
+    sync init
+  end
+  process $group_25
+    assign \fus_oper_i_alu_alu0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0
+            end
+        end
+    end
+    sync init
+  end
+  process $group_26
+    assign \fus_oper_i_alu_alu0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry
+            end
+        end
+    end
+    sync init
+  end
+  process $group_27
+    assign \fus_oper_i_alu_alu0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
+  end
+  process $group_28
+    assign \fus_oper_i_alu_alu0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_29
+    assign \fus_oper_i_alu_alu0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed
+            end
+        end
+    end
+    sync init
+  end
+  process $group_30
+    assign \fus_oper_i_alu_alu0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len
+            end
+        end
+    end
+    sync init
+  end
+  process $group_31
+    assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_32
+    assign \fus_cu_issue_i 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i \issue_i
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 4 $205
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $206
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $207
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $206
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $208
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $209
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $206
+    connect \B \pdecode2_xer_in
+    connect \Y $208
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $210
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $211
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $210
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $212
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $213
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $210
+    connect \B \pdecode2_xer_in
+    connect \Y $212
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $214
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { $212 $208 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $205
+  end
+  process $group_33
+    assign \fus_cu_rdmaskn_i 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i $205
+            end
+        end
+    end
+    sync init
+  end
+  process $group_34
+    assign \fus_oper_i_alu_cr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_35
+    assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_36
+    assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_37
+    assign \fus_oper_i_alu_cr0__read_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole
+            end
+        end
+    end
+    sync init
+  end
+  process $group_38
+    assign \fus_oper_i_alu_cr0__write_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole
+            end
+        end
+    end
+    sync init
+  end
+  process $group_39
+    assign \fus_cu_issue_i$3 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i$3 \issue_i
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 6 $215
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $216
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $215
+  end
+  process $group_40
+    assign \fus_cu_rdmaskn_i$5 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$5 $215
+            end
+        end
+    end
+    sync init
+  end
+  process $group_41
+    assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__cia \pdecode2_cia
+            end
+        end
+    end
+    sync init
+  end
+  process $group_42
+    assign \fus_oper_i_alu_branch0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_43
+    assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen$153
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i$154
-  cell \int \int
-    connect \coresync_clk \coresync_clk
-    connect \dmi__ren \dmi__ren
-    connect \dmi__data_o \dmi__data_o
-    connect \src1__ren \int_src1__ren
-    connect \src1__data_o \int_src1__data_o
-    connect \src2__ren \int_src2__ren
-    connect \src2__data_o \int_src2__data_o
-    connect \src3__ren \int_src3__ren
-    connect \src3__data_o \int_src3__data_o
-    connect \wen \int_wen
-    connect \data_i \int_data_i
-    connect \wen$1 \int_wen$153
-    connect \data_i$2 \int_data_i$154
-    connect \coresync_rst \coresync_rst
+  process $group_44
+    assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_full_rd__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \cr_full_rd__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_full_wr__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \cr_full_wr__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_data_i
-  cell \cr \cr
-    connect \coresync_clk \coresync_clk
-    connect \full_rd__ren \cr_full_rd__ren
-    connect \full_rd__data_o \cr_full_rd__data_o
-    connect \src1__ren \cr_src1__ren
-    connect \src1__data_o \cr_src1__data_o
-    connect \src2__ren \cr_src2__ren
-    connect \src2__data_o \cr_src2__data_o
-    connect \src3__ren \cr_src3__ren
-    connect \src3__data_o \cr_src3__data_o
-    connect \full_wr__wen \cr_full_wr__wen
-    connect \full_wr__data_i \cr_full_wr__data_i
-    connect \wen \cr_wen
-    connect \data_i \cr_data_i
-    connect \coresync_rst \coresync_rst
+  process $group_45
+    assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$155
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$156
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$157
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$158
-  cell \xer \xer
-    connect \coresync_clk \coresync_clk
-    connect \src1__ren \xer_src1__ren
-    connect \src1__data_o \xer_src1__data_o
-    connect \src2__ren \xer_src2__ren
-    connect \src2__data_o \xer_src2__data_o
-    connect \src3__ren \xer_src3__ren
-    connect \src3__data_o \xer_src3__data_o
-    connect \wen \xer_wen
-    connect \data_i \xer_data_i
-    connect \wen$1 \xer_wen$155
-    connect \data_i$2 \xer_data_i$156
-    connect \wen$3 \xer_wen$157
-    connect \data_i$4 \xer_data_i$158
-    connect \coresync_rst \coresync_rst
+  process $group_47
+    assign \fus_oper_i_alu_branch0__lk 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__lk \pdecode2_lk
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$159
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$160
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$161
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$162
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$163
-  cell \fast \fast
-    connect \coresync_clk \coresync_clk
-    connect \cia__ren \cia__ren
-    connect \cia__data_o \cia__data_o
-    connect \msr__ren \msr__ren
-    connect \msr__data_o \msr__data_o
-    connect \fast_nia_wen \fast_nia_wen
-    connect \wen \wen
-    connect \data_i \data_i
-    connect \src1__ren \fast_src1__ren
-    connect \src1__data_o \fast_src1__data_o
-    connect \src2__ren \fast_src2__ren
-    connect \src2__data_o \fast_src2__data_o
-    connect \wen$1 \fast_wen
-    connect \data_i$2 \fast_data_i
-    connect \wen$3 \fast_wen$159
-    connect \data_i$4 \fast_data_i$160
-    connect \data_i$5 \fast_data_i$161
-    connect \wen$6 \fast_wen$162
-    connect \data_i$7 \fast_data_i$163
-    connect \coresync_rst \coresync_rst
+  process $group_48
+    assign \fus_oper_i_alu_branch0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \spr_src__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \spr_src__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \spr_dest__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \spr_dest__data_i
-  cell \spr \spr
-    connect \coresync_clk \coresync_clk
-    connect \src__ren \spr_src__ren
-    connect \src__data_o \spr_src__data_o
-    connect \dest__wen \spr_dest__wen
-    connect \dest__data_i \spr_dest__data_i
-    connect \coresync_rst \coresync_rst
+  process $group_49
+    assign \fus_cu_issue_i$6 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i$6 \issue_i
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_ra_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 9 \rdpick_INT_ra_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 9 \rdpick_INT_ra_o
-  cell \rdpick_INT_ra \rdpick_INT_ra
-    connect \en_o \rdpick_INT_ra_en_o
-    connect \i \rdpick_INT_ra_i
-    connect \o \rdpick_INT_ra_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 3 $217
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $218
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
+    connect \Y $217
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_rb_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 \rdpick_INT_rb_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 \rdpick_INT_rb_o
-  cell \rdpick_INT_rb \rdpick_INT_rb
-    connect \en_o \rdpick_INT_rb_en_o
-    connect \i \rdpick_INT_rb_i
-    connect \o \rdpick_INT_rb_o
+  process $group_50
+    assign \fus_cu_rdmaskn_i$8 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$8 $217
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_rc_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_INT_rc_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_INT_rc_o
-  cell \rdpick_INT_rc \rdpick_INT_rc
-    connect \en_o \rdpick_INT_rc_en_o
-    connect \i \rdpick_INT_rc_i
-    connect \o \rdpick_INT_rc_o
+  process $group_51
+    assign \fus_oper_i_alu_trap0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_so_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 \rdpick_XER_xer_so_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 \rdpick_XER_xer_so_o
-  cell \rdpick_XER_xer_so \rdpick_XER_xer_so
-    connect \en_o \rdpick_XER_xer_so_en_o
-    connect \i \rdpick_XER_xer_so_i
-    connect \o \rdpick_XER_xer_so_o
+  process $group_52
+    assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_ca_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \rdpick_XER_xer_ca_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \rdpick_XER_xer_ca_o
-  cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
-    connect \en_o \rdpick_XER_xer_ca_en_o
-    connect \i \rdpick_XER_xer_ca_i
-    connect \o \rdpick_XER_xer_ca_o
+  process $group_53
+    assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_ov_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_XER_xer_ov_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_XER_xer_ov_o
-  cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov
-    connect \en_o \rdpick_XER_xer_ov_en_o
-    connect \i \rdpick_XER_xer_ov_i
-    connect \o \rdpick_XER_xer_ov_o
+  process $group_54
+    assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__msr \pdecode2_msr
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_full_cr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_full_cr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_full_cr_o
-  cell \rdpick_CR_full_cr \rdpick_CR_full_cr
-    connect \en_o \rdpick_CR_full_cr_en_o
-    connect \i \rdpick_CR_full_cr_i
-    connect \o \rdpick_CR_full_cr_o
+  process $group_55
+    assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__cia \pdecode2_cia
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_a_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_CR_cr_a_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_CR_cr_a_o
-  cell \rdpick_CR_cr_a \rdpick_CR_cr_a
-    connect \en_o \rdpick_CR_cr_a_en_o
-    connect \i \rdpick_CR_cr_a_i
-    connect \o \rdpick_CR_cr_a_o
+  process $group_56
+    assign \fus_oper_i_alu_trap0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_57
+    assign \fus_oper_i_alu_trap0__traptype 5'00000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype
+            end
+        end
+    end
+    sync init
+  end
+  process $group_58
+    assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr
+            end
+        end
+    end
+    sync init
+  end
+  process $group_59
+    assign \fus_cu_issue_i$9 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i$9 \issue_i
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_b_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_cr_b_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_cr_b_o
-  cell \rdpick_CR_cr_b \rdpick_CR_cr_b
-    connect \en_o \rdpick_CR_cr_b_en_o
-    connect \i \rdpick_CR_cr_b_i
-    connect \o \rdpick_CR_cr_b_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 4 $219
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $220
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $219
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_c_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_cr_c_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_cr_c_o
-  cell \rdpick_CR_cr_c \rdpick_CR_cr_c
-    connect \en_o \rdpick_CR_cr_c_en_o
-    connect \i \rdpick_CR_cr_c_i
-    connect \o \rdpick_CR_cr_c_o
+  process $group_60
+    assign \fus_cu_rdmaskn_i$11 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$11 $219
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_FAST_fast1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \rdpick_FAST_fast1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \rdpick_FAST_fast1_o
-  cell \rdpick_FAST_fast1 \rdpick_FAST_fast1
-    connect \en_o \rdpick_FAST_fast1_en_o
-    connect \i \rdpick_FAST_fast1_i
-    connect \o \rdpick_FAST_fast1_o
+  process $group_61
+    assign \fus_oper_i_alu_logical0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_FAST_fast2_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_FAST_fast2_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_FAST_fast2_o
-  cell \rdpick_FAST_fast2 \rdpick_FAST_fast2
-    connect \en_o \rdpick_FAST_fast2_en_o
-    connect \i \rdpick_FAST_fast2_i
-    connect \o \rdpick_FAST_fast2_o
+  process $group_62
+    assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_SPR_spr1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_SPR_spr1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_SPR_spr1_o
-  cell \rdpick_SPR_spr1 \rdpick_SPR_spr1
-    connect \en_o \rdpick_SPR_spr1_en_o
-    connect \i \rdpick_SPR_spr1_i
-    connect \o \rdpick_SPR_spr1_o
+  process $group_63
+    assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_INT_o_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 9 \wrpick_INT_o_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 9 \wrpick_INT_o_o
-  cell \wrpick_INT_o \wrpick_INT_o
-    connect \en_o \wrpick_INT_o_en_o
-    connect \i \wrpick_INT_o_i
-    connect \o \wrpick_INT_o_o
+  process $group_65
+    assign \fus_oper_i_alu_logical0__rc__rc 1'0
+    assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_INT_o1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_INT_o1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_INT_o1_o
-  cell \wrpick_INT_o1 \wrpick_INT_o1
-    connect \en_o \wrpick_INT_o1_en_o
-    connect \i \wrpick_INT_o1_i
-    connect \o \wrpick_INT_o1_o
+  process $group_67
+    assign \fus_oper_i_alu_logical0__oe__oe 1'0
+    assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_CR_full_cr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_CR_full_cr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_CR_full_cr_o
-  cell \wrpick_CR_full_cr \wrpick_CR_full_cr
-    connect \en_o \wrpick_CR_full_cr_en_o
-    connect \i \wrpick_CR_full_cr_i
-    connect \o \wrpick_CR_full_cr_o
+  process $group_69
+    assign \fus_oper_i_alu_logical0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_CR_cr_a_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 6 \wrpick_CR_cr_a_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 6 \wrpick_CR_cr_a_o
-  cell \wrpick_CR_cr_a \wrpick_CR_cr_a
-    connect \en_o \wrpick_CR_cr_a_en_o
-    connect \i \wrpick_CR_cr_a_i
-    connect \o \wrpick_CR_cr_a_o
+  process $group_70
+    assign \fus_oper_i_alu_logical0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_ca_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 \wrpick_XER_xer_ca_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 \wrpick_XER_xer_ca_o
-  cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
-    connect \en_o \wrpick_XER_xer_ca_en_o
-    connect \i \wrpick_XER_xer_ca_i
-    connect \o \wrpick_XER_xer_ca_o
+  process $group_71
+    assign \fus_oper_i_alu_logical0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_ov_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 \wrpick_XER_xer_ov_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 \wrpick_XER_xer_ov_o
-  cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
-    connect \en_o \wrpick_XER_xer_ov_en_o
-    connect \i \wrpick_XER_xer_ov_i
-    connect \o \wrpick_XER_xer_ov_o
+  process $group_72
+    assign \fus_oper_i_alu_logical0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_so_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 \wrpick_XER_xer_so_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 \wrpick_XER_xer_so_o
-  cell \wrpick_XER_xer_so \wrpick_XER_xer_so
-    connect \en_o \wrpick_XER_xer_so_en_o
-    connect \i \wrpick_XER_xer_so_i
-    connect \o \wrpick_XER_xer_so_o
+  process $group_73
+    assign \fus_oper_i_alu_logical0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_fast1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \wrpick_FAST_fast1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \wrpick_FAST_fast1_o
-  cell \wrpick_FAST_fast1 \wrpick_FAST_fast1
-    connect \en_o \wrpick_FAST_fast1_en_o
-    connect \i \wrpick_FAST_fast1_i
-    connect \o \wrpick_FAST_fast1_o
+  process $group_74
+    assign \fus_oper_i_alu_logical0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_fast2_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \wrpick_FAST_fast2_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \wrpick_FAST_fast2_o
-  cell \wrpick_FAST_fast2 \wrpick_FAST_fast2
-    connect \en_o \wrpick_FAST_fast2_en_o
-    connect \i \wrpick_FAST_fast2_i
-    connect \o \wrpick_FAST_fast2_o
+  process $group_75
+    assign \fus_oper_i_alu_logical0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_nia_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \wrpick_FAST_nia_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \wrpick_FAST_nia_o
-  cell \wrpick_FAST_nia \wrpick_FAST_nia
-    connect \en_o \wrpick_FAST_nia_en_o
-    connect \i \wrpick_FAST_nia_i
-    connect \o \wrpick_FAST_nia_o
+  process $group_76
+    assign \fus_oper_i_alu_logical0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_msr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_FAST_msr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_FAST_msr_o
-  cell \wrpick_FAST_msr \wrpick_FAST_msr
-    connect \en_o \wrpick_FAST_msr_en_o
-    connect \i \wrpick_FAST_msr_i
-    connect \o \wrpick_FAST_msr_o
+  process $group_77
+    assign \fus_oper_i_alu_logical0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_SPR_spr1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_SPR_spr1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_SPR_spr1_o
-  cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
-    connect \en_o \wrpick_SPR_spr1_en_o
-    connect \i \wrpick_SPR_spr1_i
-    connect \o \wrpick_SPR_spr1_o
+  process $group_78
+    assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_alu0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $164
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $165
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $166
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 2'10
-    connect \Y $165
+  process $group_79
+    assign \fus_cu_issue_i$12 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i$12 \issue_i
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $167
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 2 $221
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $222
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $165
-    connect \Y $164
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $221
   end
-  process $group_0
-    assign \en_alu0 1'0
-    assign \en_alu0 $164
+  process $group_80
+    assign \fus_cu_rdmaskn_i$14 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$14 $221
+            end
+        end
+    end
+    sync init
+  end
+  process $group_81
+    assign \fus_oper_i_alu_spr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_82
+    assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:128"
-  wire width 10 \fu_enable
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_branch0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_trap0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_logical0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_spr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_div0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_mul0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_shiftrot0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
-  wire width 1 \en_ldst0
-  process $group_1
-    assign \fu_enable 10'0000000000
-    assign \fu_enable [0] \en_alu0
-    assign \fu_enable [1] \en_cr0
-    assign \fu_enable [2] \en_branch0
-    assign \fu_enable [3] \en_trap0
-    assign \fu_enable [4] \en_logical0
-    assign \fu_enable [5] \en_spr0
-    assign \fu_enable [6] \en_div0
-    assign \fu_enable [7] \en_mul0
-    assign \fu_enable [8] \en_shiftrot0
-    assign \fu_enable [9] \en_ldst0
+  process $group_83
+    assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__insn \pdecode2_insn
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $168
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $169
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $170
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 7'1000000
-    connect \Y $169
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $171
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $169
-    connect \Y $168
+  process $group_84
+    assign \fus_oper_i_alu_spr0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
   end
-  process $group_2
-    assign \en_cr0 1'0
-    assign \en_cr0 $168
+  process $group_85
+    assign \fus_cu_issue_i$15 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_issue_i$15 \issue_i
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $172
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $173
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $174
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 6 $223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $224
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $225
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 6'100000
-    connect \Y $173
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $175
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $173
-    connect \Y $172
-  end
-  process $group_3
-    assign \en_branch0 1'0
-    assign \en_branch0 $172
-    sync init
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $224
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $176
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $177
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $178
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $226
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $227
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 8'10000000
-    connect \Y $177
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $179
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $177
-    connect \Y $176
-  end
-  process $group_4
-    assign \en_trap0 1'0
-    assign \en_trap0 $176
-    sync init
+    connect \A $224
+    connect \B \pdecode2_xer_in
+    connect \Y $226
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $180
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $181
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $182
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $228
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $and $229
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 5'10000
-    connect \Y $181
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $183
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $181
-    connect \Y $180
-  end
-  process $group_5
-    assign \en_logical0 1'0
-    assign \en_logical0 $180
-    sync init
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $228
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $184
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $185
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $186
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $230
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $or $231
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 11
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 11'10000000000
-    connect \Y $185
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $187
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $185
-    connect \Y $184
-  end
-  process $group_6
-    assign \en_spr0 1'0
-    assign \en_spr0 $184
-    sync init
+    connect \A $228
+    connect \B \pdecode2_xer_in
+    connect \Y $230
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $188
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $189
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $190
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $232
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $233
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 10
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 10'1000000000
-    connect \Y $189
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $191
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A $189
-    connect \Y $188
-  end
-  process $group_7
-    assign \en_div0 1'0
-    assign \en_div0 $188
-    sync init
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $232
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $192
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $193
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $194
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $234
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $235
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 9
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 9'100000000
-    connect \Y $193
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $232
+    connect \B \pdecode2_xer_in
+    connect \Y $234
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $195
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $236
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $193
-    connect \Y $192
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A { $234 $230 $226 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
+    connect \Y $223
   end
-  process $group_8
-    assign \en_mul0 1'0
-    assign \en_mul0 $192
+  process $group_86
+    assign \fus_cu_rdmaskn_i$17 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$17 $223
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $196
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $197
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $198
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 4'1000
-    connect \Y $197
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $199
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $197
-    connect \Y $196
+  process $group_87
+    assign \fus_oper_i_alu_div0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
   end
-  process $group_9
-    assign \en_shiftrot0 1'0
-    assign \en_shiftrot0 $196
+  process $group_88
+    assign \fus_oper_i_alu_div0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 1 $200
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  wire width 11 $201
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $and $202
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 3'100
-    connect \Y $201
+  process $group_89
+    assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
-  cell $reduce_bool $203
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $201
-    connect \Y $200
+  process $group_91
+    assign \fus_oper_i_alu_div0__rc__rc 1'0
+    assign \fus_oper_i_alu_div0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
   end
-  process $group_10
-    assign \en_ldst0 1'0
-    assign \en_ldst0 $200
+  process $group_93
+    assign \fus_oper_i_alu_div0__oe__oe 1'0
+    assign \fus_oper_i_alu_div0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143"
-  wire width 2 \counter
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143"
-  wire width 2 \counter$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-  wire width 1 $204
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-  cell $ne $205
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \counter
-    connect \B 1'0
-    connect \Y $204
+  process $group_95
+    assign \fus_oper_i_alu_div0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
-  wire width 3 $206
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
-  wire width 3 $207
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
-  cell $sub $208
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 3
-    connect \A \counter
-    connect \B 1'1
-    connect \Y $207
+  process $group_96
+    assign \fus_oper_i_alu_div0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  connect $206 $207
-  process $group_11
-    assign \counter$next \counter
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-    switch { $204 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  process $group_97
+    assign \fus_oper_i_alu_div0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        assign \counter$next $206 [1:0]
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__input_carry \pdecode2_input_carry
+            end
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    sync init
+  end
+  process $group_98
+    assign \fus_oper_i_alu_div0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-            assign \counter$next 2'10
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__invert_out \pdecode2_invert_out
+            end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
+    sync init
+  end
+  process $group_99
+    assign \fus_oper_i_alu_div0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        assign \counter$next 2'00
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__write_cr0 \pdecode2_write_cr0
+            end
+        end
     end
     sync init
-      update \counter 2'00
-    sync posedge \coresync_clk
-      update \counter \counter$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-  wire width 1 $209
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-  cell $ne $210
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \counter
-    connect \B 1'0
-    connect \Y $209
+  process $group_100
+    assign \fus_oper_i_alu_div0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
   end
-  process $group_12
-    assign \corebusy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
-    switch { $209 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  process $group_101
+    assign \fus_oper_i_alu_div0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        assign \corebusy_o 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__is_32bit \pdecode2_is_32bit
+            end
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    sync init
+  end
+  process $group_102
+    assign \fus_oper_i_alu_div0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-            assign \corebusy_o 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$4
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$7
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$10
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$13
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$16
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$19
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$22
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$25
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \corebusy_o \fus_cu_busy_o$28
+                assign \fus_oper_i_alu_div0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_13
-    assign \core_terminate_o$next \core_terminate_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_103
+    assign \fus_oper_i_alu_div0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-            assign \core_terminate_o$next 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_div0__data_len \pdecode2_data_len
+            end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \coresync_rst
-      case 1'1
-        assign \core_terminate_o$next 1'0
-    end
     sync init
-      update \core_terminate_o 1'0
-    sync posedge \coresync_clk
-      update \core_terminate_o \core_terminate_o$next
   end
-  process $group_14
-    assign \fus_oper_i_alu_alu0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_104
+    assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__insn_type \insn_type
+                assign \fus_oper_i_alu_div0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_15
-    assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_105
+    assign \fus_cu_issue_i$18 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit
+                assign \fus_cu_issue_i$18 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_16
-    assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 3 $237
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $238
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $239
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $238
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $240
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $241
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $238
+    connect \B \pdecode2_xer_in
+    connect \Y $240
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $242
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { $240 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $237
+  end
+  process $group_106
+    assign \fus_cu_rdmaskn_i$20 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+                assign \fus_cu_rdmaskn_i$20 $237
             end
         end
     end
     sync init
   end
-  process $group_18
-    assign \fus_oper_i_alu_alu0__rc__rc 1'0
-    assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_107
+    assign \fus_oper_i_alu_mul0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+                assign \fus_oper_i_alu_mul0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_20
-    assign \fus_oper_i_alu_alu0__oe__oe 1'0
-    assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_108
+    assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+                assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
-  process $group_22
-    assign \fus_oper_i_alu_alu0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_109
+    assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a
+                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  process $group_23
-    assign \fus_oper_i_alu_alu0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_111
+    assign \fus_oper_i_alu_mul0__rc__rc 1'0
+    assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a
+                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_24
-    assign \fus_oper_i_alu_alu0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_113
+    assign \fus_oper_i_alu_mul0__oe__oe 1'0
+    assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out
+                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_25
-    assign \fus_oper_i_alu_alu0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_115
+    assign \fus_oper_i_alu_mul0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0
+                assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a
             end
         end
     end
     sync init
   end
-  process $group_26
-    assign \fus_oper_i_alu_alu0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_116
+    assign \fus_oper_i_alu_mul0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry
+                assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a
             end
         end
     end
     sync init
   end
-  process $group_27
-    assign \fus_oper_i_alu_alu0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_117
+    assign \fus_oper_i_alu_mul0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry
+                assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out
             end
         end
     end
     sync init
   end
-  process $group_28
-    assign \fus_oper_i_alu_alu0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_118
+    assign \fus_oper_i_alu_mul0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0
             end
         end
     end
     sync init
   end
-  process $group_29
-    assign \fus_oper_i_alu_alu0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_119
+    assign \fus_oper_i_alu_mul0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed
+                assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_30
-    assign \fus_oper_i_alu_alu0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_120
+    assign \fus_oper_i_alu_mul0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len
+                assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_31
-    assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_121
+    assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_alu0__insn \pdecode2_insn
+                assign \fus_oper_i_alu_mul0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_32
-    assign \fus_cu_issue_i 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_122
+    assign \fus_cu_issue_i$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_issue_i \issue_i
+                assign \fus_cu_issue_i$21 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 4 $211
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 3 $243
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $212
+  wire width 1 $244
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $213
+  cell $and $245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -166478,1978 +157871,2669 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \pdecode2_oe
     connect \B \pdecode2_oe_ok
-    connect \Y $212
+    connect \Y $244
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $214
+  wire width 1 $246
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $215
+  cell $or $247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $212
+    connect \A $244
     connect \B \pdecode2_xer_in
-    connect \Y $214
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $216
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $217
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $216
+    connect \Y $246
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $218
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $219
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $248
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $216
-    connect \B \pdecode2_xer_in
-    connect \Y $218
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { $246 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $243
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $220
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A { $218 $214 \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $211
+  process $group_123
+    assign \fus_cu_rdmaskn_i$23 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$23 $243
+            end
+        end
+    end
+    sync init
   end
-  process $group_33
-    assign \fus_cu_rdmaskn_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_124
+    assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_rdmaskn_i $211
+                assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_34
-    assign \fus_oper_i_alu_cr0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_125
+    assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_cr0__insn_type \insn_type
+                assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
-  process $group_35
-    assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_126
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit
+                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  process $group_36
-    assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_128
+    assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0
+    assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_cr0__insn \pdecode2_insn
+                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_37
-    assign \fus_oper_i_alu_cr0__read_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_130
+    assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0
+    assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole
+                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_38
-    assign \fus_oper_i_alu_cr0__write_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_132
+    assign { } 0'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole
+                assign { } {}
             end
         end
     end
     sync init
   end
-  process $group_39
-    assign \fus_cu_issue_i$3 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_133
+    assign \fus_oper_i_alu_shift_rot0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_issue_i$3 \issue_i
+                assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 6 $221
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $222
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $221
+  process $group_134
+    assign \fus_oper_i_alu_shift_rot0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
   end
-  process $group_40
-    assign \fus_cu_rdmaskn_i$5 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_135
+    assign \fus_oper_i_alu_shift_rot0__input_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_rdmaskn_i$5 $221
+                assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr
             end
         end
     end
     sync init
   end
-  process $group_41
-    assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_136
+    assign \fus_oper_i_alu_shift_rot0__output_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__cia \pdecode2_cia
+                assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr
             end
         end
     end
     sync init
   end
-  process $group_42
-    assign \fus_oper_i_alu_branch0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_137
+    assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__insn_type \insn_type
+                assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_43
-    assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_138
+    assign \fus_oper_i_alu_shift_rot0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit
+                assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_44
-    assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_139
+    assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__insn \pdecode2_insn
+                assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_45
-    assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_140
+    assign \fus_cu_issue_i$24 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+                assign \fus_cu_issue_i$24 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_47
-    assign \fus_oper_i_alu_branch0__lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 4 $249
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $250
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $251
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $250
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $252
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $253
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $250
+    connect \B \pdecode2_xer_in
+    connect \Y $252
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $254
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { $252 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $249
+  end
+  process $group_141
+    assign \fus_cu_rdmaskn_i$26 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__lk \pdecode2_lk
+                assign \fus_cu_rdmaskn_i$26 $249
             end
         end
     end
     sync init
   end
-  process $group_48
-    assign \fus_oper_i_alu_branch0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_142
+    assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_ldst_ldst0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_49
-    assign \fus_cu_issue_i$6 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_143
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_issue_i$6 \issue_i
+                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 3 $223
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $224
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
-    connect \Y $223
+  process $group_145
+    assign \fus_oper_i_ldst_ldst0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+              case 1'1
+                assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  process $group_50
-    assign \fus_cu_rdmaskn_i$8 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_146
+    assign \fus_oper_i_ldst_ldst0__rc__rc 1'0
+    assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_rdmaskn_i$8 $223
+                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_51
-    assign \fus_oper_i_alu_trap0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_148
+    assign \fus_oper_i_ldst_ldst0__oe__oe 1'0
+    assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__insn_type \insn_type
+                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_52
-    assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_150
+    assign \fus_oper_i_ldst_ldst0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit
+                assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_53
-    assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_151
+    assign \fus_oper_i_ldst_ldst0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__insn \pdecode2_insn
+                assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_54
-    assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_152
+    assign \fus_oper_i_ldst_ldst0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__msr \pdecode2_msr
+                assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
-  process $group_55
-    assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_153
+    assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__cia \pdecode2_cia
+                assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse
             end
         end
     end
     sync init
   end
-  process $group_56
-    assign \fus_oper_i_alu_trap0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_154
+    assign \fus_oper_i_ldst_ldst0__sign_extend 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend
             end
         end
     end
     sync init
   end
-  process $group_57
-    assign \fus_oper_i_alu_trap0__traptype 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_155
+    assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype
+                assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode
             end
         end
     end
     sync init
   end
-  process $group_58
-    assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_156
+    assign \fus_cu_issue_i$27 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr
+                assign \fus_cu_issue_i$27 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_59
-    assign \fus_cu_issue_i$9 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  wire width 3 $255
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172"
+  cell $not $256
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $255
+  end
+  process $group_157
+    assign \fus_cu_rdmaskn_i$29 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
     switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166"
               case 1'1
-                assign \fus_cu_issue_i$9 \issue_i
+                assign \fus_cu_rdmaskn_i$29 $255
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 4 $225
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $226
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_ra_0
+  process $group_158
+    assign \rdflag_INT_ra_0 1'0
+    assign \rdflag_INT_ra_0 \pdecode2_reg1_ok
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $257
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $258
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [0]
+    connect \B \fu_enable [0]
+    connect \Y $257
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $259
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $260
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $257
+    connect \B \rdflag_INT_ra_0
+    connect \Y $259
+  end
+  process $group_159
+    assign \pick 1'0
+    assign \pick $259
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$261
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$262
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$263
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$264
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$265
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$266
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$267
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$268
+  process $group_160
+    assign \rdpick_INT_ra_i 9'000000000
+    assign \rdpick_INT_ra_i [0] \pick
+    assign \rdpick_INT_ra_i [1] \pick$261
+    assign \rdpick_INT_ra_i [2] \pick$262
+    assign \rdpick_INT_ra_i [3] \pick$263
+    assign \rdpick_INT_ra_i [4] \pick$264
+    assign \rdpick_INT_ra_i [5] \pick$265
+    assign \rdpick_INT_ra_i [6] \pick$266
+    assign \rdpick_INT_ra_i [7] \pick$267
+    assign \rdpick_INT_ra_i [8] \pick$268
+    sync init
+  end
+  process $group_161
+    assign \fus_cu_rd__go_i 4'0000
+    assign \fus_cu_rd__go_i [0] \rdpick_INT_ra_o [0]
+    assign \fus_cu_rd__go_i [1] \rdpick_INT_rbc_o [0]
+    assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
+    assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $269
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $270
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [0]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $269
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $271
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $272
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $271
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $273
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $274
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [1]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $273
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $275
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $276
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $275
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $277
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $278
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [2]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $277
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $279
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $280
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $279
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $281
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $282
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [3]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $281
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $283
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $284
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $283
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $285
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $286
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [4]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $285
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $287
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $288
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $287
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $289
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $290
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [5]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $289
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $291
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $292
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $291
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $293
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $294
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [6]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $293
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $295
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $296
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $295
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $297
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $298
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [7]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $297
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $299
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $300
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $299
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $301
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $302
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [8]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $301
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $303
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $304
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $303
+  end
+  process $group_162
+    assign \int_src1__ren 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $269 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $271
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $273 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $275
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $277 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $279
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $281 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $283
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $285 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $287
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $289 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $291
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $293 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $295
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $297 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $299
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $301 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \int_src1__ren $303
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $305
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $306
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [0]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $305
+  end
+  process $group_163
+    assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $305 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i \int_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $307
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $308
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [0]
+    connect \B \fu_enable [1]
+    connect \Y $307
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $309
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $310
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $307
+    connect \B \rdflag_INT_ra_0
+    connect \Y $309
+  end
+  process $group_164
+    assign \pick$261 1'0
+    assign \pick$261 $309
+    sync init
+  end
+  process $group_165
+    assign \fus_cu_rd__go_i$31 6'000000
+    assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1]
+    assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rbc_o [1]
+    assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o
+    assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0]
+    assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o
+    assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $311
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $312
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [1]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $311
+  end
+  process $group_166
+    assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $311 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i$32 \int_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $313
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $314
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$33 [0]
+    connect \B \fu_enable [3]
+    connect \Y $313
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $315
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $316
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $313
+    connect \B \rdflag_INT_ra_0
+    connect \Y $315
+  end
+  process $group_167
+    assign \pick$262 1'0
+    assign \pick$262 $315
+    sync init
+  end
+  process $group_168
+    assign \fus_cu_rd__go_i$34 4'0000
+    assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2]
+    assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rbc_o [2]
+    assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1]
+    assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $317
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $318
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [2]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $317
+  end
+  process $group_169
+    assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $317 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i$35 \int_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $319
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $320
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$36 [0]
+    connect \B \fu_enable [4]
+    connect \Y $319
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $321
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $322
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $319
+    connect \B \rdflag_INT_ra_0
+    connect \Y $321
+  end
+  process $group_170
+    assign \pick$263 1'0
+    assign \pick$263 $321
+    sync init
+  end
+  process $group_171
+    assign \fus_cu_rd__go_i$37 2'00
+    assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3]
+    assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rbc_o [3]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $323
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $324
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [3]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $323
+  end
+  process $group_172
+    assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $323 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i$38 \int_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $325
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $326
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [0]
+    connect \B \fu_enable [5]
+    connect \Y $325
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $327
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $328
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $325
+    connect \B \rdflag_INT_ra_0
+    connect \Y $327
+  end
+  process $group_173
+    assign \pick$264 1'0
+    assign \pick$264 $327
+    sync init
+  end
+  process $group_174
+    assign \fus_cu_rd__go_i$40 6'000000
+    assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [4]
+    assign \fus_cu_rd__go_i$40 [3] \rdpick_XER_xer_so_o [1]
+    assign \fus_cu_rd__go_i$40 [5] \rdpick_XER_xer_ca_o [1]
+    assign \fus_cu_rd__go_i$40 [4] \rdpick_XER_xer_ov_o
+    assign \fus_cu_rd__go_i$40 [2] \rdpick_FAST_fast1_o [2]
+    assign \fus_cu_rd__go_i$40 [1] \rdpick_SPR_spr1_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $329
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $330
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [4]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $329
+  end
+  process $group_175
+    assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $329 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i$41 \int_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $331
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $332
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$42 [0]
+    connect \B \fu_enable [6]
+    connect \Y $331
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $333
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $334
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $331
+    connect \B \rdflag_INT_ra_0
+    connect \Y $333
+  end
+  process $group_176
+    assign \pick$265 1'0
+    assign \pick$265 $333
+    sync init
+  end
+  process $group_177
+    assign \fus_cu_rd__go_i$43 3'000
+    assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [5]
+    assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rbc_o [4]
+    assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [2]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $335
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $336
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $225
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [5]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $335
   end
-  process $group_60
-    assign \fus_cu_rdmaskn_i$11 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_178
+    assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $335 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$11 $225
-            end
-        end
+        assign \fus_src1_i$44 \int_src1__data_o
     end
     sync init
   end
-  process $group_61
-    assign \fus_oper_i_alu_logical0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__insn_type \insn_type
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $337
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $338
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$45 [0]
+    connect \B \fu_enable [7]
+    connect \Y $337
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $339
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $340
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $337
+    connect \B \rdflag_INT_ra_0
+    connect \Y $339
+  end
+  process $group_179
+    assign \pick$266 1'0
+    assign \pick$266 $339
     sync init
   end
-  process $group_62
-    assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  process $group_180
+    assign \fus_cu_rd__go_i$46 3'000
+    assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [6]
+    assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rbc_o [5]
+    assign \fus_cu_rd__go_i$46 [2] \rdpick_XER_xer_so_o [3]
     sync init
   end
-  process $group_63
-    assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $341
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $342
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [6]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $341
+  end
+  process $group_181
+    assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $341 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
+        assign \fus_src1_i$47 \int_src1__data_o
     end
     sync init
   end
-  process $group_65
-    assign \fus_oper_i_alu_logical0__rc__rc 1'0
-    assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $343
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $344
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [0]
+    connect \B \fu_enable [8]
+    connect \Y $343
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $345
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $346
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $343
+    connect \B \rdflag_INT_ra_0
+    connect \Y $345
+  end
+  process $group_182
+    assign \pick$267 1'0
+    assign \pick$267 $345
     sync init
   end
-  process $group_67
-    assign \fus_oper_i_alu_logical0__oe__oe 1'0
-    assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
+  process $group_183
+    assign \fus_cu_rd__go_i$49 4'0000
+    assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_ra_o [7]
+    assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rbc_o [6]
+    assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rbc_o [8]
+    assign \fus_cu_rd__go_i$49 [3] \rdpick_XER_xer_ca_o [2]
     sync init
   end
-  process $group_69
-    assign \fus_oper_i_alu_logical0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $347
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $348
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [7]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $347
+  end
+  process $group_184
+    assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $347 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a
-            end
-        end
+        assign \fus_src1_i$50 \int_src1__data_o
     end
     sync init
   end
-  process $group_70
-    assign \fus_oper_i_alu_logical0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $349
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $350
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [0]
+    connect \B \fu_enable [9]
+    connect \Y $349
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $351
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $352
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $349
+    connect \B \rdflag_INT_ra_0
+    connect \Y $351
+  end
+  process $group_185
+    assign \pick$268 1'0
+    assign \pick$268 $351
     sync init
   end
-  process $group_71
-    assign \fus_oper_i_alu_logical0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry
-            end
-        end
-    end
+  process $group_186
+    assign \fus_cu_rd__go_i$52 3'000
+    assign \fus_cu_rd__go_i$52 [0] \rdpick_INT_ra_o [8]
+    assign \fus_cu_rd__go_i$52 [1] \rdpick_INT_rbc_o [7]
+    assign \fus_cu_rd__go_i$52 [2] \rdpick_INT_rbc_o [9]
     sync init
   end
-  process $group_72
-    assign \fus_oper_i_alu_logical0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $353
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $354
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_ra_o [8]
+    connect \B \rdpick_INT_ra_en_o
+    connect \Y $353
+  end
+  process $group_187
+    assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $353 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out
-            end
-        end
+        assign \fus_src1_i$53 \int_src1__data_o
     end
     sync init
   end
-  process $group_73
-    assign \fus_oper_i_alu_logical0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_rbc_0
+  process $group_188
+    assign \rdflag_INT_rbc_0 1'0
+    assign \rdflag_INT_rbc_0 \pdecode2_reg2_ok
     sync init
   end
-  process $group_74
-    assign \fus_oper_i_alu_logical0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_rbc_1
+  process $group_189
+    assign \rdflag_INT_rbc_1 1'0
+    assign \rdflag_INT_rbc_1 \pdecode2_reg3_ok
     sync init
   end
-  process $group_75
-    assign \fus_oper_i_alu_logical0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$355
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $356
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $357
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [1]
+    connect \B \fu_enable [0]
+    connect \Y $356
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $358
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $359
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $356
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $358
+  end
+  process $group_190
+    assign \pick$355 1'0
+    assign \pick$355 $358
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$360
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$361
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$362
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$363
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$364
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$365
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$366
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$367
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$368
+  process $group_191
+    assign \rdpick_INT_rbc_i 10'0000000000
+    assign \rdpick_INT_rbc_i [0] \pick$355
+    assign \rdpick_INT_rbc_i [1] \pick$360
+    assign \rdpick_INT_rbc_i [2] \pick$361
+    assign \rdpick_INT_rbc_i [3] \pick$362
+    assign \rdpick_INT_rbc_i [4] \pick$363
+    assign \rdpick_INT_rbc_i [5] \pick$364
+    assign \rdpick_INT_rbc_i [6] \pick$365
+    assign \rdpick_INT_rbc_i [7] \pick$366
+    assign \rdpick_INT_rbc_i [8] \pick$367
+    assign \rdpick_INT_rbc_i [9] \pick$368
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $369
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $370
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [0]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $369
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $371
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $372
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $371
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $373
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $374
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [1]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $373
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $375
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $376
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $375
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $377
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $378
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [2]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $377
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $379
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $380
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $379
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $381
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $382
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [3]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $381
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $383
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $384
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $383
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $385
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $386
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [4]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $385
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $387
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $388
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $387
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $389
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $390
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [5]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $389
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $391
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $392
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $391
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $393
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $394
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [6]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $393
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $395
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $396
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $395
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $397
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $398
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [7]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $397
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $399
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $400
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $399
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $401
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $402
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [8]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $401
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  wire width 32 $403
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  cell $sshl $404
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg3
+    connect \Y $403
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $405
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $406
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [9]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $405
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  wire width 32 $407
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  cell $sshl $408
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg3
+    connect \Y $407
+  end
+  process $group_192
+    assign \int_src3__ren 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $369 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit
-            end
-        end
+        assign \int_src3__ren $371
     end
-    sync init
-  end
-  process $group_76
-    assign \fus_oper_i_alu_logical0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $373 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed
-            end
-        end
+        assign \int_src3__ren $375
     end
-    sync init
-  end
-  process $group_77
-    assign \fus_oper_i_alu_logical0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $377 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len
-            end
-        end
+        assign \int_src3__ren $379
     end
-    sync init
-  end
-  process $group_78
-    assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $381 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__insn \pdecode2_insn
-            end
-        end
+        assign \int_src3__ren $383
     end
-    sync init
-  end
-  process $group_79
-    assign \fus_cu_issue_i$12 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $385 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$12 \issue_i
-            end
-        end
+        assign \int_src3__ren $387
     end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 2 $227
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $228
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $227
-  end
-  process $group_80
-    assign \fus_cu_rdmaskn_i$14 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $389 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$14 $227
-            end
-        end
+        assign \int_src3__ren $391
     end
-    sync init
-  end
-  process $group_81
-    assign \fus_oper_i_alu_spr0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $393 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__insn_type \insn_type
-            end
-        end
+        assign \int_src3__ren $395
     end
-    sync init
-  end
-  process $group_82
-    assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $397 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit
-            end
-        end
+        assign \int_src3__ren $399
     end
-    sync init
-  end
-  process $group_83
-    assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $401 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__insn \pdecode2_insn
-            end
-        end
+        assign \int_src3__ren $403
     end
-    sync init
-  end
-  process $group_84
-    assign \fus_oper_i_alu_spr0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $405 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit
-            end
-        end
+        assign \int_src3__ren $407
     end
     sync init
   end
-  process $group_85
-    assign \fus_cu_issue_i$15 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $409
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $410
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [0]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $409
+  end
+  process $group_193
+    assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $409 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$15 \issue_i
-            end
-        end
+        assign \fus_src2_i \int_src3__data_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 6 $229
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $230
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $231
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $411
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $230
+    connect \A \fus_cu_rd__rel_o$30 [1]
+    connect \B \fu_enable [1]
+    connect \Y $411
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $232
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $233
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $413
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $230
-    connect \B \pdecode2_xer_in
-    connect \Y $232
+    connect \A $411
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $413
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $234
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $235
+  process $group_194
+    assign \pick$360 1'0
+    assign \pick$360 $413
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $415
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $234
+    connect \A \rdpick_INT_rbc_o [1]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $415
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $236
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $237
+  process $group_195
+    assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $415 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src2_i$54 \int_src3__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $417
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $234
-    connect \B \pdecode2_xer_in
-    connect \Y $236
+    connect \A \fus_cu_rd__rel_o$33 [1]
+    connect \B \fu_enable [3]
+    connect \Y $417
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $238
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $239
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $419
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $420
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $238
+    connect \A $417
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $419
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $240
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $241
+  process $group_196
+    assign \pick$361 1'0
+    assign \pick$361 $419
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $421
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $238
-    connect \B \pdecode2_xer_in
-    connect \Y $240
+    connect \A \rdpick_INT_rbc_o [2]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $421
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $242
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A { $240 $236 $232 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
-    connect \Y $229
-  end
-  process $group_86
-    assign \fus_cu_rdmaskn_i$17 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_197
+    assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $421 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$17 $229
-            end
-        end
+        assign \fus_src2_i$55 \int_src3__data_o
     end
     sync init
   end
-  process $group_87
-    assign \fus_oper_i_alu_div0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__insn_type \insn_type
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $423
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $424
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$36 [1]
+    connect \B \fu_enable [4]
+    connect \Y $423
   end
-  process $group_88
-    assign \fus_oper_i_alu_div0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $425
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $426
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $423
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $425
   end
-  process $group_89
-    assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
-    end
+  process $group_198
+    assign \pick$362 1'0
+    assign \pick$362 $425
     sync init
   end
-  process $group_91
-    assign \fus_oper_i_alu_div0__rc__rc 1'0
-    assign \fus_oper_i_alu_div0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $427
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $428
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [3]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $427
   end
-  process $group_93
-    assign \fus_oper_i_alu_div0__oe__oe 1'0
-    assign \fus_oper_i_alu_div0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_199
+    assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $427 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
+        assign \fus_src2_i$56 \int_src3__data_o
     end
     sync init
   end
-  process $group_95
-    assign \fus_oper_i_alu_div0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__invert_a \pdecode2_invert_a
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $429
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $430
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$42 [1]
+    connect \B \fu_enable [6]
+    connect \Y $429
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $432
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $429
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $431
+  end
+  process $group_200
+    assign \pick$363 1'0
+    assign \pick$363 $431
     sync init
   end
-  process $group_96
-    assign \fus_oper_i_alu_div0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $433
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $434
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [4]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $433
+  end
+  process $group_201
+    assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $433 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__zero_a \pdecode2_zero_a
-            end
-        end
+        assign \fus_src2_i$57 \int_src3__data_o
     end
     sync init
   end
-  process $group_97
-    assign \fus_oper_i_alu_div0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__input_carry \pdecode2_input_carry
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $435
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $436
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$45 [1]
+    connect \B \fu_enable [7]
+    connect \Y $435
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $437
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $438
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $435
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $437
+  end
+  process $group_202
+    assign \pick$364 1'0
+    assign \pick$364 $437
     sync init
   end
-  process $group_98
-    assign \fus_oper_i_alu_div0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $439
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $440
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [5]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $439
+  end
+  process $group_203
+    assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $439 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__invert_out \pdecode2_invert_out
-            end
-        end
+        assign \fus_src2_i$58 \int_src3__data_o
     end
     sync init
   end
-  process $group_99
-    assign \fus_oper_i_alu_div0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__write_cr0 \pdecode2_write_cr0
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $441
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $442
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [1]
+    connect \B \fu_enable [8]
+    connect \Y $441
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $443
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $444
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $441
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $443
+  end
+  process $group_204
+    assign \pick$365 1'0
+    assign \pick$365 $443
     sync init
   end
-  process $group_100
-    assign \fus_oper_i_alu_div0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $445
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $446
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [6]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $445
+  end
+  process $group_205
+    assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $445 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__output_carry \pdecode2_output_carry
-            end
-        end
+        assign \fus_src2_i$59 \int_src3__data_o
     end
     sync init
   end
-  process $group_101
-    assign \fus_oper_i_alu_div0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $447
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $448
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [1]
+    connect \B \fu_enable [9]
+    connect \Y $447
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $449
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $450
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $447
+    connect \B \rdflag_INT_rbc_0
+    connect \Y $449
+  end
+  process $group_206
+    assign \pick$366 1'0
+    assign \pick$366 $449
     sync init
   end
-  process $group_102
-    assign \fus_oper_i_alu_div0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $451
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $452
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [7]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $451
+  end
+  process $group_207
+    assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $451 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__is_signed \pdecode2_is_signed
-            end
-        end
+        assign \fus_src2_i$60 \int_src3__data_o
     end
     sync init
   end
-  process $group_103
-    assign \fus_oper_i_alu_div0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__data_len \pdecode2_data_len
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $454
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [2]
+    connect \B \fu_enable [8]
+    connect \Y $453
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $455
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $456
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $453
+    connect \B \rdflag_INT_rbc_1
+    connect \Y $455
+  end
+  process $group_208
+    assign \pick$367 1'0
+    assign \pick$367 $455
     sync init
   end
-  process $group_104
-    assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $457
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $458
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [8]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $457
+  end
+  process $group_209
+    assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $457 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_div0__insn \pdecode2_insn
-            end
-        end
+        assign \fus_src3_i \int_src3__data_o
     end
     sync init
   end
-  process $group_105
-    assign \fus_cu_issue_i$18 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $459
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $460
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [2]
+    connect \B \fu_enable [9]
+    connect \Y $459
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $462
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $459
+    connect \B \rdflag_INT_rbc_1
+    connect \Y $461
+  end
+  process $group_210
+    assign \pick$368 1'0
+    assign \pick$368 $461
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $463
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $464
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_INT_rbc_o [9]
+    connect \B \rdpick_INT_rbc_en_o
+    connect \Y $463
+  end
+  process $group_211
+    assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $463 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$18 \issue_i
-            end
-        end
+        assign \fus_src3_i$61 \int_src3__data_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 3 $243
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_so_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $244
+  wire width 1 $465
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $245
+  cell $and $466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -168457,416 +160541,613 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \pdecode2_oe
     connect \B \pdecode2_oe_ok
-    connect \Y $244
+    connect \Y $465
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $246
+  wire width 1 $467
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $247
+  cell $or $468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $244
+    connect \A $465
     connect \B \pdecode2_xer_in
-    connect \Y $246
+    connect \Y $467
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $248
+  process $group_212
+    assign \rdflag_XER_xer_so_0 1'0
+    assign \rdflag_XER_xer_so_0 $467
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$469
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $470
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $471
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { $246 \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $243
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [2]
+    connect \B \fu_enable [0]
+    connect \Y $470
   end
-  process $group_106
-    assign \fus_cu_rdmaskn_i$20 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $472
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $473
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $470
+    connect \B \rdflag_XER_xer_so_0
+    connect \Y $472
+  end
+  process $group_213
+    assign \pick$469 1'0
+    assign \pick$469 $472
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$474
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$475
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$476
+  process $group_214
+    assign \rdpick_XER_xer_so_i 4'0000
+    assign \rdpick_XER_xer_so_i [0] \pick$469
+    assign \rdpick_XER_xer_so_i [1] \pick$474
+    assign \rdpick_XER_xer_so_i [2] \pick$475
+    assign \rdpick_XER_xer_so_i [3] \pick$476
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $477
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $478
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [0]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $477
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $479
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $480
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [1]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $479
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $481
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $482
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [2]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $481
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $483
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $484
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [3]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $483
+  end
+  process $group_215
+    assign \xer_src1__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $477 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$20 $243
-            end
-        end
+        assign \xer_src1__ren 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $479 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \xer_src1__ren 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $481 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \xer_src1__ren 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $483 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \xer_src1__ren 3'001
     end
     sync init
   end
-  process $group_107
-    assign \fus_oper_i_alu_mul0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $485
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $486
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [0]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $485
+  end
+  process $group_216
+    assign \fus_src3_i$62 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $485 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__insn_type \insn_type
-            end
-        end
+        assign \fus_src3_i$62 \xer_src1__data_o [0]
     end
     sync init
   end
-  process $group_108
-    assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $487
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $488
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [3]
+    connect \B \fu_enable [5]
+    connect \Y $487
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $489
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $490
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $487
+    connect \B \rdflag_XER_xer_so_0
+    connect \Y $489
+  end
+  process $group_217
+    assign \pick$474 1'0
+    assign \pick$474 $489
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $491
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $492
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [1]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $491
+  end
+  process $group_218
+    assign \fus_src4_i 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $491 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit
-            end
-        end
+        assign \fus_src4_i \xer_src1__data_o [0]
     end
     sync init
   end
-  process $group_109
-    assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $493
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $494
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$42 [2]
+    connect \B \fu_enable [6]
+    connect \Y $493
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $495
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $496
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $493
+    connect \B \rdflag_XER_xer_so_0
+    connect \Y $495
+  end
+  process $group_219
+    assign \pick$475 1'0
+    assign \pick$475 $495
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $497
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $498
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [2]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $497
+  end
+  process $group_220
+    assign \fus_src3_i$63 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $497 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
+        assign \fus_src3_i$63 \xer_src1__data_o [0]
     end
     sync init
   end
-  process $group_111
-    assign \fus_oper_i_alu_mul0__rc__rc 1'0
-    assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $499
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $500
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$45 [2]
+    connect \B \fu_enable [7]
+    connect \Y $499
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $501
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $502
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $499
+    connect \B \rdflag_XER_xer_so_0
+    connect \Y $501
+  end
+  process $group_221
+    assign \pick$476 1'0
+    assign \pick$476 $501
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $503
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $504
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_so_o [3]
+    connect \B \rdpick_XER_xer_so_en_o
+    connect \Y $503
+  end
+  process $group_222
+    assign \fus_src3_i$64 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $503 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
+        assign \fus_src3_i$64 \xer_src1__data_o [0]
     end
     sync init
   end
-  process $group_113
-    assign \fus_oper_i_alu_mul0__oe__oe 1'0
-    assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_ca_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $505
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $506
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $505
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $507
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $508
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $505
+    connect \B \pdecode2_xer_in
+    connect \Y $507
+  end
+  process $group_223
+    assign \rdflag_XER_xer_ca_0 1'0
+    assign \rdflag_XER_xer_ca_0 $507
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$509
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $510
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $511
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [3]
+    connect \B \fu_enable [0]
+    connect \Y $510
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $512
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $513
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $510
+    connect \B \rdflag_XER_xer_ca_0
+    connect \Y $512
+  end
+  process $group_224
+    assign \pick$509 1'0
+    assign \pick$509 $512
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$514
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$515
+  process $group_225
+    assign \rdpick_XER_xer_ca_i 3'000
+    assign \rdpick_XER_xer_ca_i [0] \pick$509
+    assign \rdpick_XER_xer_ca_i [1] \pick$514
+    assign \rdpick_XER_xer_ca_i [2] \pick$515
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $516
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $517
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [0]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $516
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $518
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $519
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [1]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $518
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $520
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $521
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [2]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $520
+  end
+  process $group_226
+    assign \xer_src2__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $516 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
+        assign \xer_src2__ren 3'010
     end
-    sync init
-  end
-  process $group_115
-    assign \fus_oper_i_alu_mul0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $518 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a
-            end
-        end
+        assign \xer_src2__ren 3'010
     end
-    sync init
-  end
-  process $group_116
-    assign \fus_oper_i_alu_mul0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $520 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a
-            end
-        end
+        assign \xer_src2__ren 3'010
     end
     sync init
   end
-  process $group_117
-    assign \fus_oper_i_alu_mul0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $522
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $523
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [0]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $522
   end
-  process $group_118
-    assign \fus_oper_i_alu_mul0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_227
+    assign \fus_src4_i$65 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $522 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0
-            end
-        end
+        assign \fus_src4_i$65 \xer_src2__data_o
     end
     sync init
   end
-  process $group_119
-    assign \fus_oper_i_alu_mul0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $524
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $525
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [5]
+    connect \B \fu_enable [5]
+    connect \Y $524
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $526
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $527
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $524
+    connect \B \rdflag_XER_xer_ca_0
+    connect \Y $526
+  end
+  process $group_228
+    assign \pick$514 1'0
+    assign \pick$514 $526
     sync init
   end
-  process $group_120
-    assign \fus_oper_i_alu_mul0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $528
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $529
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [1]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $528
+  end
+  process $group_229
+    assign \fus_src6_i 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $528 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed
-            end
-        end
+        assign \fus_src6_i \xer_src2__data_o
     end
     sync init
   end
-  process $group_121
-    assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__insn \pdecode2_insn
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $530
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $531
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [3]
+    connect \B \fu_enable [8]
+    connect \Y $530
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $532
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $533
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $530
+    connect \B \rdflag_XER_xer_ca_0
+    connect \Y $532
+  end
+  process $group_230
+    assign \pick$515 1'0
+    assign \pick$515 $532
     sync init
   end
-  process $group_122
-    assign \fus_cu_issue_i$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $534
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $535
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ca_o [2]
+    connect \B \rdpick_XER_xer_ca_en_o
+    connect \Y $534
+  end
+  process $group_231
+    assign \fus_src4_i$66 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $534 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$21 \issue_i
-            end
-        end
+        assign \fus_src4_i$66 \xer_src2__data_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 3 $249
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $250
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $251
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_ov_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $536
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $and $537
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -168874,4617 +161155,5401 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \pdecode2_oe
     connect \B \pdecode2_oe_ok
-    connect \Y $250
+    connect \Y $536
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $252
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $253
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $538
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $or $539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $250
+    connect \A $536
     connect \B \pdecode2_xer_in
-    connect \Y $252
+    connect \Y $538
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $254
+  process $group_232
+    assign \rdflag_XER_xer_ov_0 1'0
+    assign \rdflag_XER_xer_ov_0 $538
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$540
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $541
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $542
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { $252 \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $249
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [4]
+    connect \B \fu_enable [5]
+    connect \Y $541
   end
-  process $group_123
-    assign \fus_cu_rdmaskn_i$23 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$23 $249
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $543
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $544
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $541
+    connect \B \rdflag_XER_xer_ov_0
+    connect \Y $543
   end
-  process $group_124
-    assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type
-            end
-        end
-    end
+  process $group_233
+    assign \pick$540 1'0
+    assign \pick$540 $543
     sync init
   end
-  process $group_125
-    assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  process $group_234
+    assign \rdpick_XER_xer_ov_i 1'0
+    assign \rdpick_XER_xer_ov_i \pick$540
     sync init
   end
-  process $group_126
-    assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $545
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $546
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ov_o
+    connect \B \rdpick_XER_xer_ov_en_o
+    connect \Y $545
   end
-  process $group_128
-    assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0
-    assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_235
+    assign \xer_src3__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $545 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
+        assign \xer_src3__ren 3'100
     end
     sync init
   end
-  process $group_130
-    assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0
-    assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $547
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $548
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_XER_xer_ov_o
+    connect \B \rdpick_XER_xer_ov_en_o
+    connect \Y $547
   end
-  process $group_132
-    assign { } 0'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  process $group_236
+    assign \fus_src5_i 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $547 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { } {}
-            end
-        end
+        assign \fus_src5_i \xer_src3__data_o
     end
     sync init
   end
-  process $group_133
-    assign \fus_oper_i_alu_shift_rot0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_full_cr_0
+  process $group_237
+    assign \rdflag_CR_full_cr_0 1'0
+    assign \rdflag_CR_full_cr_0 \pdecode2_read_cr_whole
     sync init
   end
-  process $group_134
-    assign \fus_oper_i_alu_shift_rot0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$549
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $550
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $551
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [2]
+    connect \B \fu_enable [1]
+    connect \Y $550
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $552
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $553
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $550
+    connect \B \rdflag_CR_full_cr_0
+    connect \Y $552
+  end
+  process $group_238
+    assign \pick$549 1'0
+    assign \pick$549 $552
     sync init
   end
-  process $group_135
-    assign \fus_oper_i_alu_shift_rot0__input_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr
-            end
-        end
-    end
+  process $group_239
+    assign \rdpick_CR_full_cr_i 1'0
+    assign \rdpick_CR_full_cr_i \pick$549
     sync init
   end
-  process $group_136
-    assign \fus_oper_i_alu_shift_rot0__output_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr
-            end
-        end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $554
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $555
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_full_cr_o
+    connect \B \rdpick_CR_full_cr_en_o
+    connect \Y $554
+  end
+  process $group_240
+    assign \cr_full_rd__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $554 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \cr_full_rd__ren 8'11111111
     end
     sync init
   end
-  process $group_137
-    assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $556
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $557
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_full_cr_o
+    connect \B \rdpick_CR_full_cr_en_o
+    connect \Y $556
+  end
+  process $group_241
+    assign \fus_src3_i$67 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $556 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit
-            end
-        end
+        assign \fus_src3_i$67 \cr_full_rd__data_o
     end
     sync init
   end
-  process $group_138
-    assign \fus_oper_i_alu_shift_rot0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_a_0
+  process $group_242
+    assign \rdflag_CR_cr_a_0 1'0
+    assign \rdflag_CR_cr_a_0 \pdecode2_cr_in1_ok
     sync init
   end
-  process $group_139
-    assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$558
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $559
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $560
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [3]
+    connect \B \fu_enable [1]
+    connect \Y $559
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $561
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $562
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $559
+    connect \B \rdflag_CR_cr_a_0
+    connect \Y $561
+  end
+  process $group_243
+    assign \pick$558 1'0
+    assign \pick$558 $561
     sync init
   end
-  process $group_140
-    assign \fus_cu_issue_i$24 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$24 \issue_i
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$563
+  process $group_244
+    assign \rdpick_CR_cr_a_i 2'00
+    assign \rdpick_CR_cr_a_i [0] \pick$558
+    assign \rdpick_CR_cr_a_i [1] \pick$563
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 4 $255
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $256
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $257
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $564
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $565
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $256
+    connect \A \rdpick_CR_cr_a_o [0]
+    connect \B \rdpick_CR_cr_a_en_o
+    connect \Y $564
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $258
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $259
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $566
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 4 $567
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sub $568
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in1
+    connect \Y $567
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $569
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sshl $570
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $567
+    connect \Y $569
+  end
+  connect $566 $569
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $571
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $572
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $256
-    connect \B \pdecode2_xer_in
-    connect \Y $258
+    connect \A \rdpick_CR_cr_a_o [1]
+    connect \B \rdpick_CR_cr_a_en_o
+    connect \Y $571
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $260
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $573
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 4 $574
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sub $575
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
-    connect \A { $258 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $255
+    connect \A 3'111
+    connect \B \pdecode2_cr_in1
+    connect \Y $574
   end
-  process $group_141
-    assign \fus_cu_rdmaskn_i$26 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$26 $255
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $576
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sshl $577
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $574
+    connect \Y $576
   end
-  process $group_142
-    assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  connect $573 $576
+  process $group_245
+    assign \cr_src1__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $564 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__insn_type \insn_type
-            end
-        end
+        assign \cr_src1__ren $566 [7:0]
     end
-    sync init
-  end
-  process $group_143
-    assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $571 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
+        assign \cr_src1__ren $573 [7:0]
     end
     sync init
   end
-  process $group_145
-    assign \fus_oper_i_ldst_ldst0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $578
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $579
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_cr_a_o [0]
+    connect \B \rdpick_CR_cr_a_en_o
+    connect \Y $578
+  end
+  process $group_246
+    assign \fus_src4_i$68 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $578 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a
-            end
-        end
+        assign \fus_src4_i$68 \cr_src1__data_o
     end
     sync init
   end
-  process $group_146
-    assign \fus_oper_i_ldst_ldst0__rc__rc 1'0
-    assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $580
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $581
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$69 [2]
+    connect \B \fu_enable [2]
+    connect \Y $580
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $582
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $583
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $580
+    connect \B \rdflag_CR_cr_a_0
+    connect \Y $582
+  end
+  process $group_247
+    assign \pick$563 1'0
+    assign \pick$563 $582
     sync init
   end
-  process $group_148
-    assign \fus_oper_i_ldst_ldst0__oe__oe 1'0
-    assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
+  process $group_248
+    assign \fus_cu_rd__go_i$70 3'000
+    assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1]
+    assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0]
+    assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast1_o [3]
     sync init
   end
-  process $group_150
-    assign \fus_oper_i_ldst_ldst0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $584
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $585
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_cr_a_o [1]
+    connect \B \rdpick_CR_cr_a_en_o
+    connect \Y $584
+  end
+  process $group_249
+    assign \fus_src3_i$71 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $584 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit
-            end
-        end
+        assign \fus_src3_i$71 \cr_src1__data_o
     end
     sync init
   end
-  process $group_151
-    assign \fus_oper_i_ldst_ldst0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_b_0
+  process $group_250
+    assign \rdflag_CR_cr_b_0 1'0
+    assign \rdflag_CR_cr_b_0 \pdecode2_cr_in2_ok
     sync init
   end
-  process $group_152
-    assign \fus_oper_i_ldst_ldst0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$586
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $587
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $588
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [4]
+    connect \B \fu_enable [1]
+    connect \Y $587
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $589
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $590
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $587
+    connect \B \rdflag_CR_cr_b_0
+    connect \Y $589
+  end
+  process $group_251
+    assign \pick$586 1'0
+    assign \pick$586 $589
     sync init
   end
-  process $group_153
-    assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse
-            end
-        end
-    end
+  process $group_252
+    assign \rdpick_CR_cr_b_i 1'0
+    assign \rdpick_CR_cr_b_i \pick$586
     sync init
   end
-  process $group_154
-    assign \fus_oper_i_ldst_ldst0__sign_extend 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $591
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $592
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_cr_b_o
+    connect \B \rdpick_CR_cr_b_en_o
+    connect \Y $591
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 16 $593
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 4 $594
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  cell $sub $595
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in2
+    connect \Y $594
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 16 $596
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  cell $sshl $597
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $594
+    connect \Y $596
+  end
+  connect $593 $596
+  process $group_253
+    assign \cr_src2__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $591 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend
-            end
-        end
+        assign \cr_src2__ren $593 [7:0]
     end
     sync init
   end
-  process $group_155
-    assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $598
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $599
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_cr_b_o
+    connect \B \rdpick_CR_cr_b_en_o
+    connect \Y $598
+  end
+  process $group_254
+    assign \fus_src5_i$72 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $598 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode
-            end
-        end
+        assign \fus_src5_i$72 \cr_src2__data_o
     end
     sync init
   end
-  process $group_156
-    assign \fus_cu_issue_i$27 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_issue_i$27 \issue_i
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_c_0
+  process $group_255
+    assign \rdflag_CR_cr_c_0 1'0
+    assign \rdflag_CR_cr_c_0 \pdecode2_cr_in2_ok$1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  wire width 3 $261
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
-  cell $not $262
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$600
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $601
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $602
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $261
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [5]
+    connect \B \fu_enable [1]
+    connect \Y $601
   end
-  process $group_157
-    assign \fus_cu_rdmaskn_i$29 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-    switch { \valid }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-            switch { \fu_enable [9] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$29 $261
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $603
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $604
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $601
+    connect \B \rdflag_CR_cr_c_0
+    connect \Y $603
+  end
+  process $group_256
+    assign \pick$600 1'0
+    assign \pick$600 $603
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_INT_ra
-  process $group_158
-    assign \rdflag_INT_ra 1'0
-    assign \rdflag_INT_ra \pdecode2_reg1_ok
+  process $group_257
+    assign \rdpick_CR_cr_c_i 1'0
+    assign \rdpick_CR_cr_c_i \pick$600
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  wire width 32 $263
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  cell $sshl $264
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $605
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $606
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_CR_cr_c_o
+    connect \B \rdpick_CR_cr_c_en_o
+    connect \Y $605
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 16 $607
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 4 $608
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  cell $sub $609
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in2$2
+    connect \Y $608
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 16 $610
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  cell $sshl $611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B \pdecode2_reg1
-    connect \Y $263
+    connect \B $608
+    connect \Y $610
   end
-  process $group_159
-    assign \int_src1__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_INT_ra_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  connect $607 $610
+  process $group_258
+    assign \cr_src3__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $605 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        assign \int_src1__ren $263
+        assign \cr_src3__ren $607 [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $265
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $266
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $612
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o [0]
-    connect \B \fu_enable [0]
-    connect \Y $265
+    connect \A \rdpick_CR_cr_c_o
+    connect \B \rdpick_CR_cr_c_en_o
+    connect \Y $612
+  end
+  process $group_259
+    assign \fus_src6_i$73 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $612 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src6_i$73 \cr_src3__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_FAST_fast1_0
+  process $group_260
+    assign \rdflag_FAST_fast1_0 1'0
+    assign \rdflag_FAST_fast1_0 \pdecode2_fast1_ok
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_FAST_fast1_1
+  process $group_261
+    assign \rdflag_FAST_fast1_1 1'0
+    assign \rdflag_FAST_fast1_1 \pdecode2_fast2_ok
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $267
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $268
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$614
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $615
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $265
-    connect \B \rdflag_INT_ra
-    connect \Y $267
+    connect \A \fus_cu_rd__rel_o$69 [0]
+    connect \B \fu_enable [2]
+    connect \Y $615
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $269
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $270
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $617
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [0]
-    connect \B \fu_enable [1]
-    connect \Y $269
+    connect \A $615
+    connect \B \rdflag_FAST_fast1_0
+    connect \Y $617
+  end
+  process $group_262
+    assign \pick$614 1'0
+    assign \pick$614 $617
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$619
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$620
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$621
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$622
+  process $group_263
+    assign \rdpick_FAST_fast1_i 5'00000
+    assign \rdpick_FAST_fast1_i [0] \pick$614
+    assign \rdpick_FAST_fast1_i [1] \pick$619
+    assign \rdpick_FAST_fast1_i [2] \pick$620
+    assign \rdpick_FAST_fast1_i [3] \pick$621
+    assign \rdpick_FAST_fast1_i [4] \pick$622
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $271
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $272
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $623
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $269
-    connect \B \rdflag_INT_ra
-    connect \Y $271
+    connect \A \rdpick_FAST_fast1_o [0]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $623
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $273
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $274
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $625
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $626
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  cell $sshl $627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$33 [0]
-    connect \B \fu_enable [3]
-    connect \Y $273
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast1
+    connect \Y $626
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $275
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $276
+  connect $625 $626
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $628
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $273
-    connect \B \rdflag_INT_ra
-    connect \Y $275
+    connect \A \rdpick_FAST_fast1_o [1]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $628
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $277
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $278
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $630
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $631
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  cell $sshl $632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [0]
-    connect \B \fu_enable [4]
-    connect \Y $277
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast1
+    connect \Y $631
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $279
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $280
+  connect $630 $631
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $633
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $277
-    connect \B \rdflag_INT_ra
-    connect \Y $279
+    connect \A \rdpick_FAST_fast1_o [2]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $633
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $281
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $282
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $635
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  wire width 8 $636
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106"
+  cell $sshl $637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [0]
-    connect \B \fu_enable [5]
-    connect \Y $281
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast1
+    connect \Y $636
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $283
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $284
+  connect $635 $636
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $638
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $281
-    connect \B \rdflag_INT_ra
-    connect \Y $283
+    connect \A \rdpick_FAST_fast1_o [3]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $638
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $285
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $286
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  wire width 8 $640
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  wire width 8 $641
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  cell $sshl $642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$42 [0]
-    connect \B \fu_enable [6]
-    connect \Y $285
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast2
+    connect \Y $641
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $287
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $288
+  connect $640 $641
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $643
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $285
-    connect \B \rdflag_INT_ra
-    connect \Y $287
+    connect \A \rdpick_FAST_fast1_o [4]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $643
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $289
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $290
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  wire width 8 $645
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  wire width 8 $646
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+  cell $sshl $647
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast2
+    connect \Y $646
+  end
+  connect $645 $646
+  process $group_264
+    assign \fast_src1__ren 5'00000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $623 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fast_src1__ren $625 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $628 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fast_src1__ren $630 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $633 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fast_src1__ren $635 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $638 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fast_src1__ren $640 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $643 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fast_src1__ren $645 [4:0]
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $648
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$45 [0]
-    connect \B \fu_enable [7]
-    connect \Y $289
+    connect \A \rdpick_FAST_fast1_o [0]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $648
+  end
+  process $group_265
+    assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $648 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src1_i$74 \fast_src1__data_o
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $291
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $292
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $650
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $289
-    connect \B \rdflag_INT_ra
-    connect \Y $291
+    connect \A \fus_cu_rd__rel_o$33 [2]
+    connect \B \fu_enable [3]
+    connect \Y $650
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $293
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $294
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $652
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$48 [0]
-    connect \B \fu_enable [8]
-    connect \Y $293
+    connect \A $650
+    connect \B \rdflag_FAST_fast1_0
+    connect \Y $652
+  end
+  process $group_266
+    assign \pick$619 1'0
+    assign \pick$619 $652
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $295
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $296
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $654
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $293
-    connect \B \rdflag_INT_ra
-    connect \Y $295
+    connect \A \rdpick_FAST_fast1_o [1]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $654
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $297
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $298
+  process $group_267
+    assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $654 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src3_i$75 \fast_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $656
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$51 [0]
-    connect \B \fu_enable [9]
-    connect \Y $297
+    connect \A \fus_cu_rd__rel_o$39 [2]
+    connect \B \fu_enable [5]
+    connect \Y $656
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $299
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $300
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $658
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $297
-    connect \B \rdflag_INT_ra
-    connect \Y $299
-  end
-  process $group_160
-    assign \rdpick_INT_ra_i 9'000000000
-    assign \rdpick_INT_ra_i [0] $267
-    assign \rdpick_INT_ra_i [1] $271
-    assign \rdpick_INT_ra_i [2] $275
-    assign \rdpick_INT_ra_i [3] $279
-    assign \rdpick_INT_ra_i [4] $283
-    assign \rdpick_INT_ra_i [5] $287
-    assign \rdpick_INT_ra_i [6] $291
-    assign \rdpick_INT_ra_i [7] $295
-    assign \rdpick_INT_ra_i [8] $299
-    sync init
-  end
-  process $group_161
-    assign \fus_cu_rd__go_i 4'0000
-    assign \fus_cu_rd__go_i [0] \rdpick_INT_ra_o [0]
-    assign \fus_cu_rd__go_i [1] \rdpick_INT_rb_o [0]
-    assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
-    assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
-    sync init
-  end
-  process $group_162
-    assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i \int_src1__data_o
-    sync init
-  end
-  process $group_163
-    assign \fus_cu_rd__go_i$31 6'000000
-    assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1]
-    assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rb_o [1]
-    assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o
-    assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0]
-    assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o
-    assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o
-    sync init
-  end
-  process $group_164
-    assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$32 \int_src1__data_o
-    sync init
-  end
-  process $group_165
-    assign \fus_cu_rd__go_i$34 4'0000
-    assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2]
-    assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rb_o [2]
-    assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1]
-    assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast2_o [1]
-    sync init
-  end
-  process $group_166
-    assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$35 \int_src1__data_o
-    sync init
-  end
-  process $group_167
-    assign \fus_cu_rd__go_i$37 2'00
-    assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3]
-    assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rb_o [3]
-    sync init
-  end
-  process $group_168
-    assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$38 \int_src1__data_o
-    sync init
-  end
-  process $group_169
-    assign \fus_cu_rd__go_i$40 6'000000
-    assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [4]
-    assign \fus_cu_rd__go_i$40 [3] \rdpick_XER_xer_so_o [1]
-    assign \fus_cu_rd__go_i$40 [5] \rdpick_XER_xer_ca_o [1]
-    assign \fus_cu_rd__go_i$40 [4] \rdpick_XER_xer_ov_o
-    assign \fus_cu_rd__go_i$40 [2] \rdpick_FAST_fast1_o [2]
-    assign \fus_cu_rd__go_i$40 [1] \rdpick_SPR_spr1_o
-    sync init
-  end
-  process $group_170
-    assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$41 \int_src1__data_o
-    sync init
-  end
-  process $group_171
-    assign \fus_cu_rd__go_i$43 3'000
-    assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [5]
-    assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rb_o [4]
-    assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [2]
-    sync init
-  end
-  process $group_172
-    assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$44 \int_src1__data_o
-    sync init
-  end
-  process $group_173
-    assign \fus_cu_rd__go_i$46 3'000
-    assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [6]
-    assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rb_o [5]
-    assign \fus_cu_rd__go_i$46 [2] \rdpick_XER_xer_so_o [3]
-    sync init
-  end
-  process $group_174
-    assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$47 \int_src1__data_o
-    sync init
-  end
-  process $group_175
-    assign \fus_cu_rd__go_i$49 4'0000
-    assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_ra_o [7]
-    assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rb_o [6]
-    assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rc_o [0]
-    assign \fus_cu_rd__go_i$49 [3] \rdpick_XER_xer_ca_o [2]
-    sync init
-  end
-  process $group_176
-    assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$50 \int_src1__data_o
-    sync init
-  end
-  process $group_177
-    assign \fus_cu_rd__go_i$52 3'000
-    assign \fus_cu_rd__go_i$52 [0] \rdpick_INT_ra_o [8]
-    assign \fus_cu_rd__go_i$52 [1] \rdpick_INT_rb_o [7]
-    assign \fus_cu_rd__go_i$52 [2] \rdpick_INT_rc_o [1]
-    sync init
-  end
-  process $group_178
-    assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$53 \int_src1__data_o
-    sync init
+    connect \A $656
+    connect \B \rdflag_FAST_fast1_0
+    connect \Y $658
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_INT_rb
-  process $group_179
-    assign \rdflag_INT_rb 1'0
-    assign \rdflag_INT_rb \pdecode2_reg2_ok
+  process $group_268
+    assign \pick$620 1'0
+    assign \pick$620 $658
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  wire width 32 $301
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  cell $sshl $302
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $660
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_reg2
-    connect \Y $301
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \rdpick_FAST_fast1_o [2]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $660
   end
-  process $group_180
-    assign \int_src2__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_INT_rb_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  process $group_269
+    assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $660 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
       case 1'1
-        assign \int_src2__ren $301
+        assign \fus_src3_i$76 \fast_src1__data_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $303
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $304
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $662
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o [1]
-    connect \B \fu_enable [0]
-    connect \Y $303
+    connect \A \fus_cu_rd__rel_o$69 [1]
+    connect \B \fu_enable [2]
+    connect \Y $662
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $305
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $306
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $664
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $303
-    connect \B \rdflag_INT_rb
-    connect \Y $305
+    connect \A $662
+    connect \B \rdflag_FAST_fast1_1
+    connect \Y $664
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $307
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $308
+  process $group_270
+    assign \pick$621 1'0
+    assign \pick$621 $664
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $666
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [1]
-    connect \B \fu_enable [1]
-    connect \Y $307
+    connect \A \rdpick_FAST_fast1_o [3]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $666
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $309
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $310
+  process $group_271
+    assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $666 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src2_i$77 \fast_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $668
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $307
-    connect \B \rdflag_INT_rb
-    connect \Y $309
+    connect \A \fus_cu_rd__rel_o$33 [3]
+    connect \B \fu_enable [3]
+    connect \Y $668
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $311
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $312
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $670
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$33 [1]
-    connect \B \fu_enable [3]
-    connect \Y $311
+    connect \A $668
+    connect \B \rdflag_FAST_fast1_1
+    connect \Y $670
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $313
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $314
+  process $group_272
+    assign \pick$622 1'0
+    assign \pick$622 $670
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $672
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $311
-    connect \B \rdflag_INT_rb
-    connect \Y $313
+    connect \A \rdpick_FAST_fast1_o [4]
+    connect \B \rdpick_FAST_fast1_en_o
+    connect \Y $672
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $315
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $316
+  process $group_273
+    assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $672 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src4_i$78 \fast_src1__data_o
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_SPR_spr1_0
+  process $group_274
+    assign \rdflag_SPR_spr1_0 1'0
+    assign \rdflag_SPR_spr1_0 \pdecode2_spr1_ok
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+  wire width 1 \pick$674
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $675
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [1]
-    connect \B \fu_enable [4]
-    connect \Y $315
+    connect \A \fus_cu_rd__rel_o$39 [1]
+    connect \B \fu_enable [5]
+    connect \Y $675
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $317
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $318
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  wire width 1 $677
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+  cell $and $678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $315
-    connect \B \rdflag_INT_rb
-    connect \Y $317
+    connect \A $675
+    connect \B \rdflag_SPR_spr1_0
+    connect \Y $677
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $319
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $320
+  process $group_275
+    assign \pick$674 1'0
+    assign \pick$674 $677
+    sync init
+  end
+  process $group_276
+    assign \rdpick_SPR_spr1_i 1'0
+    assign \rdpick_SPR_spr1_i \pick$674
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158"
+  wire width 1 $memory_w_en
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $679
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$42 [1]
-    connect \B \fu_enable [6]
-    connect \Y $319
+    connect \A \rdpick_SPR_spr1_o
+    connect \B \rdpick_SPR_spr1_en_o
+    connect \Y $679
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $321
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $322
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $681
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $319
-    connect \B \rdflag_INT_rb
-    connect \Y $321
+    connect \A \wr_pick
+    connect \B \wrpick_SPR_spr1_en_o
+    connect \Y $681
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $323
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $324
+  process $group_277
+    assign $memory_w_en 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $679 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign $memory_w_en \pdecode2_spr1 [0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $681 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign $memory_w_en \pdecode2_spro [0]
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  wire width 1 $683
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+  cell $and $684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$45 [1]
-    connect \B \fu_enable [7]
-    connect \Y $323
+    connect \A \rdpick_SPR_spr1_o
+    connect \B \rdpick_SPR_spr1_en_o
+    connect \Y $683
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $325
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $326
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfiles.py:158"
+  wire width 64 $memory_w_data
+  process $group_278
+    assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+    switch { $683 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231"
+      case 1'1
+        assign \fus_src2_i$79 $memory_w_data
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_alu0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $685
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $323
-    connect \B \rdflag_INT_rb
-    connect \Y $325
+    connect \A \fus_o_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $685
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $327
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $328
+  process $group_279
+    assign \wrflag_alu0_o_0 1'0
+    assign \wrflag_alu0_o_0 $685
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $687
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$48 [1]
-    connect \B \fu_enable [8]
-    connect \Y $327
+    connect \A \fus_cu_wr__rel_o [0]
+    connect \B \fu_enable [0]
+    connect \Y $687
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $329
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $330
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $689
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $327
-    connect \B \rdflag_INT_rb
-    connect \Y $329
+    connect \A \fus_cu_wr__rel_o$81 [0]
+    connect \B \fu_enable [1]
+    connect \Y $689
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $331
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $332
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $691
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$51 [1]
-    connect \B \fu_enable [9]
-    connect \Y $331
+    connect \A \fus_cu_wr__rel_o$84 [0]
+    connect \B \fu_enable [3]
+    connect \Y $691
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $333
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $334
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $693
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $331
-    connect \B \rdflag_INT_rb
-    connect \Y $333
-  end
-  process $group_181
-    assign \rdpick_INT_rb_i 8'00000000
-    assign \rdpick_INT_rb_i [0] $305
-    assign \rdpick_INT_rb_i [1] $309
-    assign \rdpick_INT_rb_i [2] $313
-    assign \rdpick_INT_rb_i [3] $317
-    assign \rdpick_INT_rb_i [4] $321
-    assign \rdpick_INT_rb_i [5] $325
-    assign \rdpick_INT_rb_i [6] $329
-    assign \rdpick_INT_rb_i [7] $333
-    sync init
-  end
-  process $group_182
-    assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i \int_src2__data_o
-    sync init
-  end
-  process $group_183
-    assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$54 \int_src2__data_o
-    sync init
-  end
-  process $group_184
-    assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$55 \int_src2__data_o
-    sync init
-  end
-  process $group_185
-    assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$56 \int_src2__data_o
-    sync init
-  end
-  process $group_186
-    assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$57 \int_src2__data_o
-    sync init
-  end
-  process $group_187
-    assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$58 \int_src2__data_o
-    sync init
-  end
-  process $group_188
-    assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$59 \int_src2__data_o
-    sync init
-  end
-  process $group_189
-    assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$60 \int_src2__data_o
-    sync init
+    connect \A \fus_cu_wr__rel_o$87 [0]
+    connect \B \fu_enable [4]
+    connect \Y $693
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_INT_rc
-  process $group_190
-    assign \rdflag_INT_rc 1'0
-    assign \rdflag_INT_rc \pdecode2_reg3_ok
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $695
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $696
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$90 [0]
+    connect \B \fu_enable [5]
+    connect \Y $695
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  wire width 32 $335
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  cell $sshl $336
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $697
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_reg3
-    connect \Y $335
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$93 [0]
+    connect \B \fu_enable [6]
+    connect \Y $697
   end
-  process $group_191
-    assign \int_src3__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_INT_rc_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-      case 1'1
-        assign \int_src3__ren $335
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $699
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $700
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$96 [0]
+    connect \B \fu_enable [7]
+    connect \Y $699
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $337
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $338
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $701
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$48 [2]
+    connect \A \fus_cu_wr__rel_o$99 [0]
     connect \B \fu_enable [8]
-    connect \Y $337
+    connect \Y $701
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $339
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $340
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $703
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $337
-    connect \B \rdflag_INT_rc
-    connect \Y $339
+    connect \A \fus_cu_wr__rel_o$101 [0]
+    connect \B \fu_enable [9]
+    connect \Y $703
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $341
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $342
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $705
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$51 [2]
+    connect \A \fus_cu_wr__rel_o$101 [1]
     connect \B \fu_enable [9]
-    connect \Y $341
+    connect \Y $705
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $343
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $344
+  process $group_280
+    assign \wrpick_INT_o_i 10'0000000000
+    assign \wrpick_INT_o_i [0] $687
+    assign \wrpick_INT_o_i [1] $689
+    assign \wrpick_INT_o_i [2] $691
+    assign \wrpick_INT_o_i [3] $693
+    assign \wrpick_INT_o_i [4] $695
+    assign \wrpick_INT_o_i [5] $697
+    assign \wrpick_INT_o_i [6] $699
+    assign \wrpick_INT_o_i [7] $701
+    assign \wrpick_INT_o_i [8] $703
+    assign \wrpick_INT_o_i [9] $705
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$707
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $708
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $341
-    connect \B \rdflag_INT_rc
-    connect \Y $343
-  end
-  process $group_192
-    assign \rdpick_INT_rc_i 2'00
-    assign \rdpick_INT_rc_i [0] $339
-    assign \rdpick_INT_rc_i [1] $343
-    sync init
+    connect \A \wrpick_INT_o_o [0]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $708
   end
-  process $group_193
-    assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i \int_src3__data_o
+  process $group_281
+    assign \wr_pick$707 1'0
+    assign \wr_pick$707 $708
     sync init
   end
-  process $group_194
-    assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$61 \int_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$next
+  process $group_282
+    assign \wr_pick_dly$next \wr_pick_dly
+    assign \wr_pick_dly$next \wr_pick$707
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$next 1'0
+    end
     sync init
+      update \wr_pick_dly 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly \wr_pick_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_XER_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $345
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $346
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $710
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $345
+    connect \A \wr_pick_dly
+    connect \Y $710
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $347
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $348
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $712
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $345
-    connect \B \pdecode2_xer_in
-    connect \Y $347
-  end
-  process $group_195
-    assign \rdflag_XER_xer_so 1'0
-    assign \rdflag_XER_xer_so $347
-    sync init
+    connect \A \wr_pick$707
+    connect \B $710
+    connect \Y $712
   end
-  process $group_196
-    assign \xer_src1__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_XER_xer_so_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-      case 1'1
-        assign \xer_src1__ren 3'001
-    end
+  process $group_283
+    assign \wr_pick_rise 1'0
+    assign \wr_pick_rise $712
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$714
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$715
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$716
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$717
+  process $group_284
+    assign \fus_cu_wr__go_i 5'00000
+    assign \fus_cu_wr__go_i [0] \wr_pick_rise
+    assign \fus_cu_wr__go_i [1] \wr_pick_rise$714
+    assign \fus_cu_wr__go_i [2] \wr_pick_rise$715
+    assign \fus_cu_wr__go_i [3] \wr_pick_rise$716
+    assign \fus_cu_wr__go_i [4] \wr_pick_rise$717
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $349
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $350
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $718
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o [2]
-    connect \B \fu_enable [0]
-    connect \Y $349
+    connect \A \wr_pick$707
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $718
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $351
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $352
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $720
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $349
-    connect \B \rdflag_XER_xer_so
-    connect \Y $351
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $720
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $353
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $354
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$722
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $723
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $724
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [3]
-    connect \B \fu_enable [5]
-    connect \Y $353
+    connect \A \wr_pick$722
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $723
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $355
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $356
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $725
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $726
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $353
-    connect \B \rdflag_XER_xer_so
-    connect \Y $355
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $725
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $357
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $358
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$727
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $728
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$42 [2]
-    connect \B \fu_enable [6]
-    connect \Y $357
+    connect \A \wr_pick$727
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $728
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $359
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $360
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $730
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $731
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $357
-    connect \B \rdflag_XER_xer_so
-    connect \Y $359
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $730
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $361
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $362
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$732
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $733
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $734
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$45 [2]
-    connect \B \fu_enable [7]
-    connect \Y $361
+    connect \A \wr_pick$732
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $733
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $735
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $736
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $735
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $363
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $364
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$737
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $738
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $739
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $361
-    connect \B \rdflag_XER_xer_so
-    connect \Y $363
-  end
-  process $group_197
-    assign \rdpick_XER_xer_so_i 4'0000
-    assign \rdpick_XER_xer_so_i [0] $351
-    assign \rdpick_XER_xer_so_i [1] $355
-    assign \rdpick_XER_xer_so_i [2] $359
-    assign \rdpick_XER_xer_so_i [3] $363
-    sync init
-  end
-  process $group_198
-    assign \fus_src3_i$62 1'0
-    assign \fus_src3_i$62 \xer_src1__data_o [0]
-    sync init
-  end
-  process $group_199
-    assign \fus_src4_i 1'0
-    assign \fus_src4_i \xer_src1__data_o [0]
-    sync init
-  end
-  process $group_200
-    assign \fus_src3_i$63 1'0
-    assign \fus_src3_i$63 \xer_src1__data_o [0]
-    sync init
-  end
-  process $group_201
-    assign \fus_src3_i$64 1'0
-    assign \fus_src3_i$64 \xer_src1__data_o [0]
-    sync init
+    connect \A \wr_pick$737
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $738
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_XER_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $365
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $366
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $740
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $741
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $365
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $740
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $367
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $368
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$742
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $743
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $744
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $365
-    connect \B \pdecode2_xer_in
-    connect \Y $367
-  end
-  process $group_202
-    assign \rdflag_XER_xer_ca 1'0
-    assign \rdflag_XER_xer_ca $367
-    sync init
+    connect \A \wr_pick$742
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $743
   end
-  process $group_203
-    assign \xer_src2__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_XER_xer_ca_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-      case 1'1
-        assign \xer_src2__ren 3'010
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $745
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $746
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $745
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $369
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $370
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$747
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $748
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $749
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o [3]
-    connect \B \fu_enable [0]
-    connect \Y $369
+    connect \A \wr_pick$747
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $748
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $750
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $751
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $750
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $371
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $372
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$752
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $753
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $754
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $369
-    connect \B \rdflag_XER_xer_ca
-    connect \Y $371
+    connect \A \wr_pick$752
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $753
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $373
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $374
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $755
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $756
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $755
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$757
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $758
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $759
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [5]
-    connect \B \fu_enable [5]
-    connect \Y $373
+    connect \A \wr_pick$757
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $758
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  wire width 32 $760
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:129"
+  cell $sshl $761
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_rego
+    connect \Y $760
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $375
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $376
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$762
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $763
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $764
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $373
-    connect \B \rdflag_XER_xer_ca
-    connect \Y $375
+    connect \A \wr_pick$762
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $763
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $377
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $378
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131"
+  wire width 32 $765
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:131"
+  cell $sshl $766
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_ea
+    connect \Y $765
+  end
+  process $group_285
+    assign \int_wen 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $718 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $720
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $723 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $725
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $728 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $730
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $733 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $735
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $738 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $740
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $743 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $745
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $748 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $750
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $753 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $755
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $758 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $760
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $763 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \int_wen $765
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_cr0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $767
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $768
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$48 [3]
-    connect \B \fu_enable [8]
-    connect \Y $377
+    connect \A \fus_o_ok$80
+    connect \B \fus_cu_busy_o$4
+    connect \Y $767
+  end
+  process $group_286
+    assign \wrflag_cr0_o_0 1'0
+    assign \wrflag_cr0_o_0 $767
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $379
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $380
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $769
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $770
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $377
-    connect \B \rdflag_XER_xer_ca
-    connect \Y $379
+    connect \A \wrpick_INT_o_o [1]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $769
   end
-  process $group_204
-    assign \rdpick_XER_xer_ca_i 3'000
-    assign \rdpick_XER_xer_ca_i [0] $371
-    assign \rdpick_XER_xer_ca_i [1] $375
-    assign \rdpick_XER_xer_ca_i [2] $379
+  process $group_287
+    assign \wr_pick$722 1'0
+    assign \wr_pick$722 $769
     sync init
   end
-  process $group_205
-    assign \fus_src4_i$65 2'00
-    assign \fus_src4_i$65 \xer_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$771
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$771$next
+  process $group_288
+    assign \wr_pick_dly$771$next \wr_pick_dly$771
+    assign \wr_pick_dly$771$next \wr_pick$722
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$771$next 1'0
+    end
     sync init
+      update \wr_pick_dly$771 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$771 \wr_pick_dly$771$next
   end
-  process $group_206
-    assign \fus_src6_i 2'00
-    assign \fus_src6_i \xer_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$772
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $773
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $774
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$771
+    connect \Y $773
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $775
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $776
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$722
+    connect \B $773
+    connect \Y $775
+  end
+  process $group_289
+    assign \wr_pick_rise$772 1'0
+    assign \wr_pick_rise$772 $775
     sync init
   end
-  process $group_207
-    assign \fus_src4_i$66 2'00
-    assign \fus_src4_i$66 \xer_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$777
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$778
+  process $group_290
+    assign \fus_cu_wr__go_i$82 3'000
+    assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$772
+    assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$777
+    assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$778
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_XER_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $381
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $382
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_trap0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $779
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $780
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $381
+    connect \A \fus_o_ok$83
+    connect \B \fus_cu_busy_o$10
+    connect \Y $779
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $383
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $384
+  process $group_291
+    assign \wrflag_trap0_o_0 1'0
+    assign \wrflag_trap0_o_0 $779
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $781
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $782
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $381
-    connect \B \pdecode2_xer_in
-    connect \Y $383
+    connect \A \wrpick_INT_o_o [2]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $781
   end
-  process $group_208
-    assign \rdflag_XER_xer_ov 1'0
-    assign \rdflag_XER_xer_ov $383
+  process $group_292
+    assign \wr_pick$727 1'0
+    assign \wr_pick$727 $781
     sync init
   end
-  process $group_209
-    assign \xer_src3__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$783
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$783$next
+  process $group_293
+    assign \wr_pick_dly$783$next \wr_pick_dly$783
+    assign \wr_pick_dly$783$next \wr_pick$727
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \xer_src3__ren 3'100
+        assign \wr_pick_dly$783$next 1'0
     end
     sync init
+      update \wr_pick_dly$783 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$783 \wr_pick_dly$783$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $385
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $386
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$784
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $785
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $786
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$783
+    connect \Y $785
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $787
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $788
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [4]
-    connect \B \fu_enable [5]
-    connect \Y $385
+    connect \A \wr_pick$727
+    connect \B $785
+    connect \Y $787
+  end
+  process $group_294
+    assign \wr_pick_rise$784 1'0
+    assign \wr_pick_rise$784 $787
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$789
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$790
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$791
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$792
+  process $group_295
+    assign \fus_cu_wr__go_i$85 5'00000
+    assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$784
+    assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$789
+    assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$790
+    assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$791
+    assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$792
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $387
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $388
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_logical0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $793
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $794
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $385
-    connect \B \rdflag_XER_xer_ov
-    connect \Y $387
+    connect \A \fus_o_ok$86
+    connect \B \fus_cu_busy_o$13
+    connect \Y $793
   end
-  process $group_210
-    assign \rdpick_XER_xer_ov_i 1'0
-    assign \rdpick_XER_xer_ov_i $387
+  process $group_296
+    assign \wrflag_logical0_o_0 1'0
+    assign \wrflag_logical0_o_0 $793
     sync init
   end
-  process $group_211
-    assign \fus_src5_i 2'00
-    assign \fus_src5_i \xer_src3__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $795
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $796
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_INT_o_o [3]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $795
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_CR_full_cr
-  process $group_212
-    assign \rdflag_CR_full_cr 1'0
-    assign \rdflag_CR_full_cr \pdecode2_read_cr_whole
+  process $group_297
+    assign \wr_pick$732 1'0
+    assign \wr_pick$732 $795
     sync init
   end
-  process $group_213
-    assign \cr_full_rd__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$797
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$797$next
+  process $group_298
+    assign \wr_pick_dly$797$next \wr_pick_dly$797
+    assign \wr_pick_dly$797$next \wr_pick$732
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \cr_full_rd__ren 8'11111111
+        assign \wr_pick_dly$797$next 1'0
     end
     sync init
+      update \wr_pick_dly$797 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$797 \wr_pick_dly$797$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $389
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $390
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$798
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $799
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $800
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [2]
-    connect \B \fu_enable [1]
-    connect \Y $389
+    connect \A \wr_pick_dly$797
+    connect \Y $799
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $391
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $392
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $801
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $802
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $389
-    connect \B \rdflag_CR_full_cr
-    connect \Y $391
-  end
-  process $group_214
-    assign \rdpick_CR_full_cr_i 1'0
-    assign \rdpick_CR_full_cr_i $391
-    sync init
+    connect \A \wr_pick$732
+    connect \B $799
+    connect \Y $801
   end
-  process $group_215
-    assign \fus_src3_i$67 32'00000000000000000000000000000000
-    assign \fus_src3_i$67 \cr_full_rd__data_o
+  process $group_299
+    assign \wr_pick_rise$798 1'0
+    assign \wr_pick_rise$798 $801
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_CR_cr_a
-  process $group_216
-    assign \rdflag_CR_cr_a 1'0
-    assign \rdflag_CR_cr_a \pdecode2_cr_in1_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$803
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$804
+  process $group_300
+    assign \fus_cu_wr__go_i$88 3'000
+    assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$798
+    assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$803
+    assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$804
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $393
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 4 $394
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sub $395
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_spr0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $805
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $806
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_in1
-    connect \Y $394
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_o_ok$89
+    connect \B \fus_cu_busy_o$16
+    connect \Y $805
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $396
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sshl $397
+  process $group_301
+    assign \wrflag_spr0_o_0 1'0
+    assign \wrflag_spr0_o_0 $805
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $807
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $808
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $394
-    connect \Y $396
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_INT_o_o [4]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $807
   end
-  connect $393 $396
-  process $group_217
-    assign \cr_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  process $group_302
+    assign \wr_pick$737 1'0
+    assign \wr_pick$737 $807
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$809
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$809$next
+  process $group_303
+    assign \wr_pick_dly$809$next \wr_pick_dly$809
+    assign \wr_pick_dly$809$next \wr_pick$737
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \cr_src1__ren $393 [7:0]
+        assign \wr_pick_dly$809$next 1'0
     end
     sync init
+      update \wr_pick_dly$809 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$809 \wr_pick_dly$809$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $398
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $399
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$810
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $811
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $812
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [3]
-    connect \B \fu_enable [1]
-    connect \Y $398
+    connect \A \wr_pick_dly$809
+    connect \Y $811
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $400
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $401
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $813
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $814
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $398
-    connect \B \rdflag_CR_cr_a
-    connect \Y $400
+    connect \A \wr_pick$737
+    connect \B $811
+    connect \Y $813
+  end
+  process $group_304
+    assign \wr_pick_rise$810 1'0
+    assign \wr_pick_rise$810 $813
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$815
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$816
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$817
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$818
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$819
+  process $group_305
+    assign \fus_cu_wr__go_i$91 6'000000
+    assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$810
+    assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$815
+    assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$816
+    assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$817
+    assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$818
+    assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$819
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $402
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $403
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_div0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $820
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $821
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$69 [2]
-    connect \B \fu_enable [2]
-    connect \Y $402
+    connect \A \fus_o_ok$92
+    connect \B \fus_cu_busy_o$19
+    connect \Y $820
+  end
+  process $group_306
+    assign \wrflag_div0_o_0 1'0
+    assign \wrflag_div0_o_0 $820
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $404
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $405
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $822
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $823
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $402
-    connect \B \rdflag_CR_cr_a
-    connect \Y $404
+    connect \A \wrpick_INT_o_o [5]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $822
   end
-  process $group_218
-    assign \rdpick_CR_cr_a_i 2'00
-    assign \rdpick_CR_cr_a_i [0] $400
-    assign \rdpick_CR_cr_a_i [1] $404
+  process $group_307
+    assign \wr_pick$742 1'0
+    assign \wr_pick$742 $822
     sync init
   end
-  process $group_219
-    assign \fus_src4_i$68 4'0000
-    assign \fus_src4_i$68 \cr_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$824
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$824$next
+  process $group_308
+    assign \wr_pick_dly$824$next \wr_pick_dly$824
+    assign \wr_pick_dly$824$next \wr_pick$742
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$824$next 1'0
+    end
     sync init
+      update \wr_pick_dly$824 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$824 \wr_pick_dly$824$next
   end
-  process $group_220
-    assign \fus_cu_rd__go_i$70 3'000
-    assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1]
-    assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0]
-    assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast2_o [0]
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$825
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $826
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $827
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$824
+    connect \Y $826
   end
-  process $group_221
-    assign \fus_src3_i$71 4'0000
-    assign \fus_src3_i$71 \cr_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $828
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $829
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$742
+    connect \B $826
+    connect \Y $828
+  end
+  process $group_309
+    assign \wr_pick_rise$825 1'0
+    assign \wr_pick_rise$825 $828
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_CR_cr_b
-  process $group_222
-    assign \rdflag_CR_cr_b 1'0
-    assign \rdflag_CR_cr_b \pdecode2_cr_in2_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$830
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$831
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$832
+  process $group_310
+    assign \fus_cu_wr__go_i$94 4'0000
+    assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$825
+    assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$830
+    assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$831
+    assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$832
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $406
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 4 $407
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sub $408
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_mul0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $833
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $834
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_in2
-    connect \Y $407
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_o_ok$95
+    connect \B \fus_cu_busy_o$22
+    connect \Y $833
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $409
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sshl $410
+  process $group_311
+    assign \wrflag_mul0_o_0 1'0
+    assign \wrflag_mul0_o_0 $833
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $835
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $836
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $407
-    connect \Y $409
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_INT_o_o [6]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $835
   end
-  connect $406 $409
-  process $group_223
-    assign \cr_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_CR_cr_b_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  process $group_312
+    assign \wr_pick$747 1'0
+    assign \wr_pick$747 $835
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$837
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$837$next
+  process $group_313
+    assign \wr_pick_dly$837$next \wr_pick_dly$837
+    assign \wr_pick_dly$837$next \wr_pick$747
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \cr_src2__ren $406 [7:0]
+        assign \wr_pick_dly$837$next 1'0
     end
     sync init
+      update \wr_pick_dly$837 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$837 \wr_pick_dly$837$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $411
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $412
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$838
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $839
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $840
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [4]
-    connect \B \fu_enable [1]
-    connect \Y $411
+    connect \A \wr_pick_dly$837
+    connect \Y $839
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $413
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $414
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $841
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $842
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $411
-    connect \B \rdflag_CR_cr_b
-    connect \Y $413
-  end
-  process $group_224
-    assign \rdpick_CR_cr_b_i 1'0
-    assign \rdpick_CR_cr_b_i $413
-    sync init
+    connect \A \wr_pick$747
+    connect \B $839
+    connect \Y $841
   end
-  process $group_225
-    assign \fus_src5_i$72 4'0000
-    assign \fus_src5_i$72 \cr_src2__data_o
+  process $group_314
+    assign \wr_pick_rise$838 1'0
+    assign \wr_pick_rise$838 $841
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_CR_cr_c
-  process $group_226
-    assign \rdflag_CR_cr_c 1'0
-    assign \rdflag_CR_cr_c \pdecode2_cr_in2_ok$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$843
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$844
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$845
+  process $group_315
+    assign \fus_cu_wr__go_i$97 4'0000
+    assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$838
+    assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$843
+    assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$844
+    assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$845
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $415
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 4 $416
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sub $417
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_shiftrot0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $846
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $847
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_in2$2
-    connect \Y $416
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_o_ok$98
+    connect \B \fus_cu_busy_o$25
+    connect \Y $846
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $418
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sshl $419
+  process $group_316
+    assign \wrflag_shiftrot0_o_0 1'0
+    assign \wrflag_shiftrot0_o_0 $846
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $848
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $849
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $416
-    connect \Y $418
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_INT_o_o [7]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $848
   end
-  connect $415 $418
-  process $group_227
-    assign \cr_src3__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_CR_cr_c_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  process $group_317
+    assign \wr_pick$752 1'0
+    assign \wr_pick$752 $848
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$850
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$850$next
+  process $group_318
+    assign \wr_pick_dly$850$next \wr_pick_dly$850
+    assign \wr_pick_dly$850$next \wr_pick$752
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \cr_src3__ren $415 [7:0]
+        assign \wr_pick_dly$850$next 1'0
     end
     sync init
+      update \wr_pick_dly$850 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$850 \wr_pick_dly$850$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $420
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $421
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$851
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $852
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $853
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [5]
-    connect \B \fu_enable [1]
-    connect \Y $420
+    connect \A \wr_pick_dly$850
+    connect \Y $852
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $422
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $423
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $854
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $855
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $420
-    connect \B \rdflag_CR_cr_c
-    connect \Y $422
+    connect \A \wr_pick$752
+    connect \B $852
+    connect \Y $854
   end
-  process $group_228
-    assign \rdpick_CR_cr_c_i 1'0
-    assign \rdpick_CR_cr_c_i $422
+  process $group_319
+    assign \wr_pick_rise$851 1'0
+    assign \wr_pick_rise$851 $854
     sync init
   end
-  process $group_229
-    assign \fus_src6_i$73 4'0000
-    assign \fus_src6_i$73 \cr_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$856
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$857
+  process $group_320
+    assign \fus_cu_wr__go_i$100 3'000
+    assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$851
+    assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$856
+    assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$857
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_FAST_fast1
-  process $group_230
-    assign \rdflag_FAST_fast1 1'0
-    assign \rdflag_FAST_fast1 \pdecode2_fast1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_ldst0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $858
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $859
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \o_ok
+    connect \B \fus_cu_busy_o$28
+    connect \Y $858
+  end
+  process $group_321
+    assign \wrflag_ldst0_o_0 1'0
+    assign \wrflag_ldst0_o_0 $858
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  wire width 8 $424
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  cell $sshl $425
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $860
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $861
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fast1
-    connect \Y $424
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_INT_o_o [8]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $860
   end
-  process $group_231
-    assign \fast_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  process $group_322
+    assign \wr_pick$757 1'0
+    assign \wr_pick$757 $860
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$862
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$862$next
+  process $group_323
+    assign \wr_pick_dly$862$next \wr_pick_dly$862
+    assign \wr_pick_dly$862$next \wr_pick$757
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \fast_src1__ren $424
+        assign \wr_pick_dly$862$next 1'0
     end
     sync init
+      update \wr_pick_dly$862 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$862 \wr_pick_dly$862$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $426
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $427
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$863
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $864
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $865
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$69 [0]
-    connect \B \fu_enable [2]
-    connect \Y $426
+    connect \A \wr_pick_dly$862
+    connect \Y $864
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $428
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $429
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $866
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $867
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $426
-    connect \B \rdflag_FAST_fast1
-    connect \Y $428
+    connect \A \wr_pick$757
+    connect \B $864
+    connect \Y $866
+  end
+  process $group_324
+    assign \wr_pick_rise$863 1'0
+    assign \wr_pick_rise$863 $866
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$868
+  process $group_325
+    assign \fus_cu_wr__go_i$102 2'00
+    assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$863
+    assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$868
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $430
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_ldst0_o_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \ea_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $869
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $870
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$33 [2]
-    connect \B \fu_enable [3]
-    connect \Y $430
+    connect \A \ea_ok
+    connect \B \fus_cu_busy_o$28
+    connect \Y $869
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $432
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $433
+  process $group_326
+    assign \wrflag_ldst0_o_1 1'0
+    assign \wrflag_ldst0_o_1 $869
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $871
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $872
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $430
-    connect \B \rdflag_FAST_fast1
-    connect \Y $432
+    connect \A \wrpick_INT_o_o [9]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $871
+  end
+  process $group_327
+    assign \wr_pick$762 1'0
+    assign \wr_pick$762 $871
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$873
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$873$next
+  process $group_328
+    assign \wr_pick_dly$873$next \wr_pick_dly$873
+    assign \wr_pick_dly$873$next \wr_pick$762
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$873$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$873 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$873 \wr_pick_dly$873$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $434
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $435
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $874
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $875
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [2]
-    connect \B \fu_enable [5]
-    connect \Y $434
+    connect \A \wr_pick_dly$873
+    connect \Y $874
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $436
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $437
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $876
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $877
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $434
-    connect \B \rdflag_FAST_fast1
-    connect \Y $436
+    connect \A \wr_pick$762
+    connect \B $874
+    connect \Y $876
   end
-  process $group_232
-    assign \rdpick_FAST_fast1_i 3'000
-    assign \rdpick_FAST_fast1_i [0] $428
-    assign \rdpick_FAST_fast1_i [1] $432
-    assign \rdpick_FAST_fast1_i [2] $436
+  process $group_329
+    assign \wr_pick_rise$868 1'0
+    assign \wr_pick_rise$868 $876
     sync init
   end
-  process $group_233
-    assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$74 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $878
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $879
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $880
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o
+    connect \B \fus_dest1_o$103
+    connect \Y $879
   end
-  process $group_234
-    assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$75 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $881
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $882
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$105
+    connect \B \fus_dest1_o$106
+    connect \Y $881
   end
-  process $group_235
-    assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$76 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $883
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $884
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$104
+    connect \B $881
+    connect \Y $883
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_FAST_fast2
-  process $group_236
-    assign \rdflag_FAST_fast2 1'0
-    assign \rdflag_FAST_fast2 \pdecode2_fast2_ok
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $885
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $886
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $879
+    connect \B $883
+    connect \Y $885
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  wire width 8 $438
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  cell $sshl $439
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $887
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $888
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fast2
-    connect \Y $438
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$107
+    connect \B \fus_dest1_o$108
+    connect \Y $887
   end
-  process $group_237
-    assign \fast_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-      case 1'1
-        assign \fast_src2__ren $438
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 65 $889
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $890
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 65
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A { \o_ok \fus_o }
+    connect \B { \ea_ok \fus_ea }
+    connect \Y $889
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $440
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $441
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $891
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $892
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$69 [1]
-    connect \B \fu_enable [2]
-    connect \Y $440
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A \fus_dest1_o$109
+    connect \B $889
+    connect \Y $891
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $442
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $443
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $893
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $894
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $440
-    connect \B \rdflag_FAST_fast2
-    connect \Y $442
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A $887
+    connect \B $891
+    connect \Y $893
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $895
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $896
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A $885
+    connect \B $893
+    connect \Y $895
+  end
+  connect $878 $895
+  process $group_330
+    assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \int_data_i $878 [63:0]
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $444
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $445
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_cr0_full_cr_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $897
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $898
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$33 [3]
-    connect \B \fu_enable [3]
-    connect \Y $444
+    connect \A \fus_full_cr_ok
+    connect \B \fus_cu_busy_o$4
+    connect \Y $897
+  end
+  process $group_331
+    assign \wrflag_cr0_full_cr_1 1'0
+    assign \wrflag_cr0_full_cr_1 $897
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $446
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $447
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $899
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $900
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $444
-    connect \B \rdflag_FAST_fast2
-    connect \Y $446
-  end
-  process $group_238
-    assign \rdpick_FAST_fast2_i 2'00
-    assign \rdpick_FAST_fast2_i [0] $442
-    assign \rdpick_FAST_fast2_i [1] $446
-    sync init
+    connect \A \fus_cu_wr__rel_o$81 [1]
+    connect \B \fu_enable [1]
+    connect \Y $899
   end
-  process $group_239
-    assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$77 \fast_src2__data_o
+  process $group_332
+    assign \wrpick_CR_full_cr_i 1'0
+    assign \wrpick_CR_full_cr_i $899
     sync init
   end
-  process $group_240
-    assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src4_i$78 \fast_src2__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$901
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $902
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $903
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_CR_full_cr_o
+    connect \B \wrpick_CR_full_cr_en_o
+    connect \Y $902
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
-  wire width 1 \rdflag_SPR_spr1
-  process $group_241
-    assign \rdflag_SPR_spr1 1'0
-    assign \rdflag_SPR_spr1 \pdecode2_spr1_ok
+  process $group_333
+    assign \wr_pick$901 1'0
+    assign \wr_pick$901 $902
     sync init
   end
-  process $group_242
-    assign \spr_src__ren 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
-    switch { \rdpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$904
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$904$next
+  process $group_334
+    assign \wr_pick_dly$904$next \wr_pick_dly$904
+    assign \wr_pick_dly$904$next \wr_pick$901
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \spr_src__ren \pdecode2_spr1 [0]
+        assign \wr_pick_dly$904$next 1'0
     end
     sync init
+      update \wr_pick_dly$904 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$904 \wr_pick_dly$904$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $448
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $449
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $905
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $906
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [1]
-    connect \B \fu_enable [5]
-    connect \Y $448
+    connect \A \wr_pick_dly$904
+    connect \Y $905
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  wire width 1 $450
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-  cell $and $451
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $907
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $908
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $448
-    connect \B \rdflag_SPR_spr1
-    connect \Y $450
-  end
-  process $group_243
-    assign \rdpick_SPR_spr1_i 1'0
-    assign \rdpick_SPR_spr1_i $450
-    sync init
+    connect \A \wr_pick$901
+    connect \B $905
+    connect \Y $907
   end
-  process $group_244
-    assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$79 \spr_src__data_o
+  process $group_335
+    assign \wr_pick_rise$777 1'0
+    assign \wr_pick_rise$777 $907
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  wire width 32 $452
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  cell $sshl $453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $909
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $910
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_rego
-    connect \Y $452
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$901
+    connect \B \wrpick_CR_full_cr_en_o
+    connect \Y $909
   end
-  process $group_245
-    assign \int_wen 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_INT_o_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  process $group_336
+    assign \cr_full_wr__wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $909 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
       case 1'1
-        assign \int_wen $452
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \int_wen 32'00000000000000000000000000000000
+        assign \cr_full_wr__wen 8'11111111
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_alu0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $454
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $455
+  process $group_337
+    assign \cr_full_wr__data_i 32'00000000000000000000000000000000
+    assign \cr_full_wr__data_i \fus_dest2_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_alu0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $911
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $912
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok
+    connect \A \fus_cr_a_ok
     connect \B \fus_cu_busy_o
-    connect \Y $454
+    connect \Y $911
   end
-  process $group_246
-    assign \wrflag_alu0_o_0 1'0
-    assign \wrflag_alu0_o_0 $454
+  process $group_338
+    assign \wrflag_alu0_cr_a_1 1'0
+    assign \wrflag_alu0_cr_a_1 $911
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $456
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $457
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $913
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $914
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [0]
+    connect \A \fus_cu_wr__rel_o [1]
     connect \B \fu_enable [0]
-    connect \Y $456
+    connect \Y $913
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $458
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $459
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $915
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $916
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$81 [0]
+    connect \A \fus_cu_wr__rel_o$81 [2]
     connect \B \fu_enable [1]
-    connect \Y $458
+    connect \Y $915
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $460
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $917
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $918
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$84 [0]
-    connect \B \fu_enable [3]
-    connect \Y $460
+    connect \A \fus_cu_wr__rel_o$87 [1]
+    connect \B \fu_enable [4]
+    connect \Y $917
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $462
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $463
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $919
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $920
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$87 [0]
-    connect \B \fu_enable [4]
-    connect \Y $462
+    connect \A \fus_cu_wr__rel_o$93 [1]
+    connect \B \fu_enable [6]
+    connect \Y $919
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $464
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $465
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $921
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $922
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [0]
-    connect \B \fu_enable [5]
-    connect \Y $464
+    connect \A \fus_cu_wr__rel_o$96 [1]
+    connect \B \fu_enable [7]
+    connect \Y $921
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $466
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $467
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $923
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $924
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$93 [0]
-    connect \B \fu_enable [6]
-    connect \Y $466
+    connect \A \fus_cu_wr__rel_o$99 [1]
+    connect \B \fu_enable [8]
+    connect \Y $923
+  end
+  process $group_339
+    assign \wrpick_CR_cr_a_i 6'000000
+    assign \wrpick_CR_cr_a_i [0] $913
+    assign \wrpick_CR_cr_a_i [1] $915
+    assign \wrpick_CR_cr_a_i [2] $917
+    assign \wrpick_CR_cr_a_i [3] $919
+    assign \wrpick_CR_cr_a_i [4] $921
+    assign \wrpick_CR_cr_a_i [5] $923
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $468
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $469
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$925
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $926
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $927
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$96 [0]
-    connect \B \fu_enable [7]
-    connect \Y $468
+    connect \A \wrpick_CR_cr_a_o [0]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $926
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $470
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $471
+  process $group_340
+    assign \wr_pick$925 1'0
+    assign \wr_pick$925 $926
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$928
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$928$next
+  process $group_341
+    assign \wr_pick_dly$928$next \wr_pick_dly$928
+    assign \wr_pick_dly$928$next \wr_pick$925
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$928$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$928 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$928 \wr_pick_dly$928$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $929
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $930
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$99 [0]
-    connect \B \fu_enable [8]
-    connect \Y $470
+    connect \A \wr_pick_dly$928
+    connect \Y $929
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $472
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $473
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $931
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $932
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$101 [0]
-    connect \B \fu_enable [9]
-    connect \Y $472
+    connect \A \wr_pick$925
+    connect \B $929
+    connect \Y $931
   end
-  process $group_247
-    assign \wrpick_INT_o_i 9'000000000
-    assign \wrpick_INT_o_i [0] $456
-    assign \wrpick_INT_o_i [1] $458
-    assign \wrpick_INT_o_i [2] $460
-    assign \wrpick_INT_o_i [3] $462
-    assign \wrpick_INT_o_i [4] $464
-    assign \wrpick_INT_o_i [5] $466
-    assign \wrpick_INT_o_i [6] $468
-    assign \wrpick_INT_o_i [7] $470
-    assign \wrpick_INT_o_i [8] $472
+  process $group_342
+    assign \wr_pick_rise$714 1'0
+    assign \wr_pick_rise$714 $931
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $474
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $475
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $933
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $934
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [0]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $474
+    connect \A \wr_pick$925
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $933
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $935
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $936
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $937
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $936
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $938
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $939
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $936
+    connect \Y $938
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $476
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $477
+  connect $935 $938
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$940
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $941
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $942
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [0]
+    connect \A \wr_pick$940
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $476
+    connect \Y $941
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $943
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $944
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $945
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $944
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $946
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $947
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $944
+    connect \Y $946
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $478
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $479
+  connect $943 $946
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$948
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $949
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $950
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [0]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $478
+    connect \A \wr_pick$948
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $949
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $480
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $481
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $951
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $952
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $953
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $952
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $954
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $955
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $952
+    connect \Y $954
+  end
+  connect $951 $954
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$956
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $957
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $958
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [0]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $480
+    connect \A \wr_pick$956
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $957
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $959
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $960
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $961
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $960
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $962
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $963
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $960
+    connect \Y $962
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $482
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $483
+  connect $959 $962
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$964
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $965
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $966
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [0]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $482
+    connect \A \wr_pick$964
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $965
   end
-  process $group_248
-    assign \fus_cu_wr__go_i 5'00000
-    assign \fus_cu_wr__go_i [0] $474
-    assign \fus_cu_wr__go_i [1] $476
-    assign \fus_cu_wr__go_i [2] $478
-    assign \fus_cu_wr__go_i [3] $480
-    assign \fus_cu_wr__go_i [4] $482
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $967
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $968
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $969
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $968
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_cr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $484
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $485
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $970
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $971
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $968
+    connect \Y $970
+  end
+  connect $967 $970
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$972
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $973
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $974
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$80
-    connect \B \fus_cu_busy_o$4
-    connect \Y $484
+    connect \A \wr_pick$972
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $973
   end
-  process $group_249
-    assign \wrflag_cr0_o_0 1'0
-    assign \wrflag_cr0_o_0 $484
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $975
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 4 $976
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sub $977
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_out
+    connect \Y $976
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  wire width 16 $978
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141"
+  cell $sshl $979
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $976
+    connect \Y $978
+  end
+  connect $975 $978
+  process $group_343
+    assign \cr_wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $933 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $935 [7:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $941 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $943 [7:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $949 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $951 [7:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $957 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $959 [7:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $965 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $967 [7:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $973 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \cr_wen $975 [7:0]
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $486
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $487
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_cr0_cr_a_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $980
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $981
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [1]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $486
+    connect \A \fus_cr_a_ok$110
+    connect \B \fus_cu_busy_o$4
+    connect \Y $980
+  end
+  process $group_344
+    assign \wrflag_cr0_cr_a_2 1'0
+    assign \wrflag_cr0_cr_a_2 $980
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $488
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $489
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $982
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $983
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_full_cr_o
-    connect \B \wrpick_CR_full_cr_en_o
-    connect \Y $488
+    connect \A \wrpick_CR_cr_a_o [1]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $982
+  end
+  process $group_345
+    assign \wr_pick$940 1'0
+    assign \wr_pick$940 $982
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$984
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$984$next
+  process $group_346
+    assign \wr_pick_dly$984$next \wr_pick_dly$984
+    assign \wr_pick_dly$984$next \wr_pick$940
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$984$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$984 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$984 \wr_pick_dly$984$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $490
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $491
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $985
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $986
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [1]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $490
-  end
-  process $group_250
-    assign \fus_cu_wr__go_i$82 3'000
-    assign \fus_cu_wr__go_i$82 [0] $486
-    assign \fus_cu_wr__go_i$82 [1] $488
-    assign \fus_cu_wr__go_i$82 [2] $490
-    sync init
+    connect \A \wr_pick_dly$984
+    connect \Y $985
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_trap0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $492
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $493
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $987
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $988
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$83
-    connect \B \fus_cu_busy_o$10
-    connect \Y $492
+    connect \A \wr_pick$940
+    connect \B $985
+    connect \Y $987
   end
-  process $group_251
-    assign \wrflag_trap0_o_0 1'0
-    assign \wrflag_trap0_o_0 $492
+  process $group_347
+    assign \wr_pick_rise$778 1'0
+    assign \wr_pick_rise$778 $987
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $494
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $495
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_logical0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $989
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $990
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [2]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $494
+    connect \A \fus_cr_a_ok$111
+    connect \B \fus_cu_busy_o$13
+    connect \Y $989
+  end
+  process $group_348
+    assign \wrflag_logical0_cr_a_1 1'0
+    assign \wrflag_logical0_cr_a_1 $989
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $496
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $497
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $991
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $992
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast1_o [1]
-    connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $496
+    connect \A \wrpick_CR_cr_a_o [2]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $991
+  end
+  process $group_349
+    assign \wr_pick$948 1'0
+    assign \wr_pick$948 $991
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$993
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$993$next
+  process $group_350
+    assign \wr_pick_dly$993$next \wr_pick_dly$993
+    assign \wr_pick_dly$993$next \wr_pick$948
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$993$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$993 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$993 \wr_pick_dly$993$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $498
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $499
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $994
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $995
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast2_o [1]
-    connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $498
+    connect \A \wr_pick_dly$993
+    connect \Y $994
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $500
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $501
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $996
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $997
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_nia_o [1]
-    connect \B \wrpick_FAST_nia_en_o
-    connect \Y $500
+    connect \A \wr_pick$948
+    connect \B $994
+    connect \Y $996
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $502
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $503
+  process $group_351
+    assign \wr_pick_rise$803 1'0
+    assign \wr_pick_rise$803 $996
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_div0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $998
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $999
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_msr_o
-    connect \B \wrpick_FAST_msr_en_o
-    connect \Y $502
+    connect \A \fus_cr_a_ok$112
+    connect \B \fus_cu_busy_o$19
+    connect \Y $998
   end
-  process $group_252
-    assign \fus_cu_wr__go_i$85 5'00000
-    assign \fus_cu_wr__go_i$85 [0] $494
-    assign \fus_cu_wr__go_i$85 [1] $496
-    assign \fus_cu_wr__go_i$85 [2] $498
-    assign \fus_cu_wr__go_i$85 [3] $500
-    assign \fus_cu_wr__go_i$85 [4] $502
+  process $group_352
+    assign \wrflag_div0_cr_a_1 1'0
+    assign \wrflag_div0_cr_a_1 $998
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_logical0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $504
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $505
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1000
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1001
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$86
-    connect \B \fus_cu_busy_o$13
-    connect \Y $504
+    connect \A \wrpick_CR_cr_a_o [3]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $1000
   end
-  process $group_253
-    assign \wrflag_logical0_o_0 1'0
-    assign \wrflag_logical0_o_0 $504
+  process $group_353
+    assign \wr_pick$956 1'0
+    assign \wr_pick$956 $1000
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1002
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1002$next
+  process $group_354
+    assign \wr_pick_dly$1002$next \wr_pick_dly$1002
+    assign \wr_pick_dly$1002$next \wr_pick$956
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1002$next 1'0
+    end
     sync init
+      update \wr_pick_dly$1002 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1002 \wr_pick_dly$1002$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $506
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $507
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1003
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1004
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [3]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $506
+    connect \A \wr_pick_dly$1002
+    connect \Y $1003
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $508
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $509
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1005
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1006
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [2]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $508
+    connect \A \wr_pick$956
+    connect \B $1003
+    connect \Y $1005
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $510
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $511
+  process $group_355
+    assign \wr_pick_rise$830 1'0
+    assign \wr_pick_rise$830 $1005
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_mul0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1007
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1008
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [1]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $510
+    connect \A \fus_cr_a_ok$113
+    connect \B \fus_cu_busy_o$22
+    connect \Y $1007
   end
-  process $group_254
-    assign \fus_cu_wr__go_i$88 3'000
-    assign \fus_cu_wr__go_i$88 [0] $506
-    assign \fus_cu_wr__go_i$88 [1] $508
-    assign \fus_cu_wr__go_i$88 [2] $510
+  process $group_356
+    assign \wrflag_mul0_cr_a_1 1'0
+    assign \wrflag_mul0_cr_a_1 $1007
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_spr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $512
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $513
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1009
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1010
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$89
-    connect \B \fus_cu_busy_o$16
-    connect \Y $512
+    connect \A \wrpick_CR_cr_a_o [4]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $1009
   end
-  process $group_255
-    assign \wrflag_spr0_o_0 1'0
-    assign \wrflag_spr0_o_0 $512
+  process $group_357
+    assign \wr_pick$964 1'0
+    assign \wr_pick$964 $1009
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1011
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1011$next
+  process $group_358
+    assign \wr_pick_dly$1011$next \wr_pick_dly$1011
+    assign \wr_pick_dly$1011$next \wr_pick$964
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1011$next 1'0
+    end
     sync init
+      update \wr_pick_dly$1011 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1011 \wr_pick_dly$1011$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $514
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $515
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1012
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1013
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [4]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $514
+    connect \A \wr_pick_dly$1011
+    connect \Y $1012
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $516
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $517
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1014
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1015
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [2]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $516
+    connect \A \wr_pick$964
+    connect \B $1012
+    connect \Y $1014
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $518
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $519
+  process $group_359
+    assign \wr_pick_rise$843 1'0
+    assign \wr_pick_rise$843 $1014
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_shiftrot0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1016
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1017
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [1]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $518
+    connect \A \fus_cr_a_ok$114
+    connect \B \fus_cu_busy_o$25
+    connect \Y $1016
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $520
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $521
+  process $group_360
+    assign \wrflag_shiftrot0_cr_a_1 1'0
+    assign \wrflag_shiftrot0_cr_a_1 $1016
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1018
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1019
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [1]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $520
+    connect \A \wrpick_CR_cr_a_o [5]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $1018
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $522
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $523
+  process $group_361
+    assign \wr_pick$972 1'0
+    assign \wr_pick$972 $1018
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1020
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1020$next
+  process $group_362
+    assign \wr_pick_dly$1020$next \wr_pick_dly$1020
+    assign \wr_pick_dly$1020$next \wr_pick$972
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1020$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1020 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1020 \wr_pick_dly$1020$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1021
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1022
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast1_o [2]
-    connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $522
+    connect \A \wr_pick_dly$1020
+    connect \Y $1021
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $524
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $525
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1023
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1024
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_SPR_spr1_o
-    connect \B \wrpick_SPR_spr1_en_o
-    connect \Y $524
+    connect \A \wr_pick$972
+    connect \B $1021
+    connect \Y $1023
   end
-  process $group_256
-    assign \fus_cu_wr__go_i$91 6'000000
-    assign \fus_cu_wr__go_i$91 [0] $514
-    assign \fus_cu_wr__go_i$91 [5] $516
-    assign \fus_cu_wr__go_i$91 [4] $518
-    assign \fus_cu_wr__go_i$91 [3] $520
-    assign \fus_cu_wr__go_i$91 [2] $522
-    assign \fus_cu_wr__go_i$91 [1] $524
+  process $group_363
+    assign \wr_pick_rise$856 1'0
+    assign \wr_pick_rise$856 $1023
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_div0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $526
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $527
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 4 $1025
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $1026
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$92
-    connect \B \fus_cu_busy_o$19
-    connect \Y $526
-  end
-  process $group_257
-    assign \wrflag_div0_o_0 1'0
-    assign \wrflag_div0_o_0 $526
-    sync init
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest3_o
+    connect \B \fus_dest2_o$116
+    connect \Y $1025
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $528
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $529
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $1027
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1028
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [5]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $528
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$115
+    connect \B $1025
+    connect \Y $1027
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $530
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $531
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 4 $1029
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $1030
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [3]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $530
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$118
+    connect \B \fus_dest2_o$119
+    connect \Y $1029
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $532
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $533
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $1031
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1032
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [2]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $532
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$117
+    connect \B $1029
+    connect \Y $1031
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $534
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $535
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $1033
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1034
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [2]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $534
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $1027
+    connect \B $1031
+    connect \Y $1033
   end
-  process $group_258
-    assign \fus_cu_wr__go_i$94 4'0000
-    assign \fus_cu_wr__go_i$94 [0] $528
-    assign \fus_cu_wr__go_i$94 [1] $530
-    assign \fus_cu_wr__go_i$94 [2] $532
-    assign \fus_cu_wr__go_i$94 [3] $534
+  process $group_364
+    assign \cr_data_i 4'0000
+    assign \cr_data_i $1033
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_mul0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $536
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $537
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_alu0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1035
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1036
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$95
-    connect \B \fus_cu_busy_o$22
-    connect \Y $536
+    connect \A \fus_xer_ca_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $1035
   end
-  process $group_259
-    assign \wrflag_mul0_o_0 1'0
-    assign \wrflag_mul0_o_0 $536
+  process $group_365
+    assign \wrflag_alu0_xer_ca_2 1'0
+    assign \wrflag_alu0_xer_ca_2 $1035
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $538
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $539
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1037
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1038
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [6]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $538
+    connect \A \fus_cu_wr__rel_o [2]
+    connect \B \fu_enable [0]
+    connect \Y $1037
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $540
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $541
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1039
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1040
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [4]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $540
+    connect \A \fus_cu_wr__rel_o$87 [2]
+    connect \B \fu_enable [4]
+    connect \Y $1039
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $542
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $543
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1041
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1042
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [3]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $542
+    connect \A \fus_cu_wr__rel_o$90 [5]
+    connect \B \fu_enable [5]
+    connect \Y $1041
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $544
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $545
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1043
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1044
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [3]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $544
+    connect \A \fus_cu_wr__rel_o$99 [2]
+    connect \B \fu_enable [8]
+    connect \Y $1043
   end
-  process $group_260
-    assign \fus_cu_wr__go_i$97 4'0000
-    assign \fus_cu_wr__go_i$97 [0] $538
-    assign \fus_cu_wr__go_i$97 [1] $540
-    assign \fus_cu_wr__go_i$97 [2] $542
-    assign \fus_cu_wr__go_i$97 [3] $544
+  process $group_366
+    assign \wrpick_XER_xer_ca_i 4'0000
+    assign \wrpick_XER_xer_ca_i [0] $1037
+    assign \wrpick_XER_xer_ca_i [1] $1039
+    assign \wrpick_XER_xer_ca_i [2] $1041
+    assign \wrpick_XER_xer_ca_i [3] $1043
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_shiftrot0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $546
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $547
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1045
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1046
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1047
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$98
-    connect \B \fus_cu_busy_o$25
-    connect \Y $546
+    connect \A \wrpick_XER_xer_ca_o [0]
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1046
   end
-  process $group_261
-    assign \wrflag_shiftrot0_o_0 1'0
-    assign \wrflag_shiftrot0_o_0 $546
+  process $group_367
+    assign \wr_pick$1045 1'0
+    assign \wr_pick$1045 $1046
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1048
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1048$next
+  process $group_368
+    assign \wr_pick_dly$1048$next \wr_pick_dly$1048
+    assign \wr_pick_dly$1048$next \wr_pick$1045
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1048$next 1'0
+    end
     sync init
+      update \wr_pick_dly$1048 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1048 \wr_pick_dly$1048$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $548
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $549
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1049
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1050
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [7]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $548
+    connect \A \wr_pick_dly$1048
+    connect \Y $1049
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $550
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $551
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1051
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1052
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [5]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $550
+    connect \A \wr_pick$1045
+    connect \B $1049
+    connect \Y $1051
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $552
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $553
+  process $group_369
+    assign \wr_pick_rise$715 1'0
+    assign \wr_pick_rise$715 $1051
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1053
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1054
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [3]
+    connect \A \wr_pick$1045
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $552
-  end
-  process $group_262
-    assign \fus_cu_wr__go_i$100 3'000
-    assign \fus_cu_wr__go_i$100 [0] $548
-    assign \fus_cu_wr__go_i$100 [1] $550
-    assign \fus_cu_wr__go_i$100 [2] $552
-    sync init
+    connect \Y $1053
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_ldst0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $554
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $555
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1055
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1056
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1057
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \o_ok
-    connect \B \fus_cu_busy_o$28
-    connect \Y $554
-  end
-  process $group_263
-    assign \wrflag_ldst0_o_0 1'0
-    assign \wrflag_ldst0_o_0 $554
-    sync init
+    connect \A \wr_pick$1055
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1056
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $556
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $557
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1058
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1059
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1060
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [8]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $556
+    connect \A \wr_pick$1058
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1059
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $558
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $559
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1061
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1062
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1063
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o1_o
-    connect \B \wrpick_INT_o1_en_o
-    connect \Y $558
+    connect \A \wr_pick$1061
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1062
   end
-  process $group_264
-    assign \fus_cu_wr__go_i$102 2'00
-    assign \fus_cu_wr__go_i$102 [0] $556
-    assign \fus_cu_wr__go_i$102 [1] $558
+  process $group_370
+    assign \xer_wen 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1053 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen 3'010
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1056 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen 3'010
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1059 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen 3'010
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1062 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen 3'010
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $560
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $561
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $562
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_logical0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1064
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1065
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o
-    connect \B \fus_dest1_o$103
-    connect \Y $561
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_xer_ca_ok$120
+    connect \B \fus_cu_busy_o$13
+    connect \Y $1064
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $563
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $564
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$104
-    connect \B \fus_dest1_o$105
-    connect \Y $563
+  process $group_371
+    assign \wrflag_logical0_xer_ca_2 1'0
+    assign \wrflag_logical0_xer_ca_2 $1064
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $565
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $566
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1066
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1067
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $561
-    connect \B $563
-    connect \Y $565
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_XER_xer_ca_o [1]
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1066
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $567
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $568
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$106
-    connect \B \fus_dest1_o$107
-    connect \Y $567
+  process $group_372
+    assign \wr_pick$1055 1'0
+    assign \wr_pick$1055 $1066
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 65 $569
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $570
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A \fus_dest1_o$109
-    connect \B { \o_ok \fus_o }
-    connect \Y $569
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1068
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1068$next
+  process $group_373
+    assign \wr_pick_dly$1068$next \wr_pick_dly$1068
+    assign \wr_pick_dly$1068$next \wr_pick$1055
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1068$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1068 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1068 \wr_pick_dly$1068$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $571
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $572
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1069
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1070
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A \fus_dest1_o$108
-    connect \B $569
-    connect \Y $571
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1068
+    connect \Y $1069
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $573
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $574
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1071
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1072
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A $567
-    connect \B $571
-    connect \Y $573
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1055
+    connect \B $1069
+    connect \Y $1071
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $575
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $576
+  process $group_374
+    assign \wr_pick_rise$804 1'0
+    assign \wr_pick_rise$804 $1071
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_spr0_xer_ca_5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1073
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1074
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A $565
-    connect \B $573
-    connect \Y $575
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_xer_ca_ok$121
+    connect \B \fus_cu_busy_o$16
+    connect \Y $1073
   end
-  connect $560 $575
-  process $group_265
-    assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i $560 [63:0]
+  process $group_375
+    assign \wrflag_spr0_xer_ca_5 1'0
+    assign \wrflag_spr0_xer_ca_5 $1073
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  wire width 32 $577
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  cell $sshl $578
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1075
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1076
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_ea
-    connect \Y $577
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_XER_xer_ca_o [2]
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1075
   end
-  process $group_266
-    assign \int_wen$153 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_INT_o1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  process $group_376
+    assign \wr_pick$1058 1'0
+    assign \wr_pick$1058 $1075
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1077
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1077$next
+  process $group_377
+    assign \wr_pick_dly$1077$next \wr_pick_dly$1077
+    assign \wr_pick_dly$1077$next \wr_pick$1058
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \int_wen$153 $577
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \int_wen$153 32'00000000000000000000000000000000
+        assign \wr_pick_dly$1077$next 1'0
     end
     sync init
+      update \wr_pick_dly$1077 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1077 \wr_pick_dly$1077$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_ldst0_o1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $579
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $580
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1078
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1079
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1077
+    connect \Y $1078
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1080
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1081
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ea_ok
-    connect \B \fus_cu_busy_o$28
-    connect \Y $579
+    connect \A \wr_pick$1058
+    connect \B $1078
+    connect \Y $1080
   end
-  process $group_267
-    assign \wrflag_ldst0_o1_1 1'0
-    assign \wrflag_ldst0_o1_1 $579
+  process $group_378
+    assign \wr_pick_rise$815 1'0
+    assign \wr_pick_rise$815 $1080
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $581
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $582
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_shiftrot0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1082
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1083
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$101 [1]
-    connect \B \fu_enable [9]
-    connect \Y $581
+    connect \A \fus_xer_ca_ok$122
+    connect \B \fus_cu_busy_o$25
+    connect \Y $1082
   end
-  process $group_268
-    assign \wrpick_INT_o1_i 1'0
-    assign \wrpick_INT_o1_i $581
+  process $group_379
+    assign \wrflag_shiftrot0_xer_ca_2 1'0
+    assign \wrflag_shiftrot0_xer_ca_2 $1082
     sync init
   end
-  process $group_269
-    assign \int_data_i$154 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i$154 { \ea_ok \fus_ea } [63:0]
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1084
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1085
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_XER_xer_ca_o [3]
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $1084
+  end
+  process $group_380
+    assign \wr_pick$1061 1'0
+    assign \wr_pick$1061 $1084
     sync init
   end
-  process $group_270
-    assign \cr_full_wr__wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1086
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1086$next
+  process $group_381
+    assign \wr_pick_dly$1086$next \wr_pick_dly$1086
+    assign \wr_pick_dly$1086$next \wr_pick$1061
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \cr_full_wr__wen 8'11111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \cr_full_wr__wen 8'00000000
+        assign \wr_pick_dly$1086$next 1'0
     end
     sync init
+      update \wr_pick_dly$1086 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1086 \wr_pick_dly$1086$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_cr0_full_cr_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $583
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $584
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1087
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1088
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_full_cr_ok
-    connect \B \fus_cu_busy_o$4
-    connect \Y $583
-  end
-  process $group_271
-    assign \wrflag_cr0_full_cr_1 1'0
-    assign \wrflag_cr0_full_cr_1 $583
-    sync init
+    connect \A \wr_pick_dly$1086
+    connect \Y $1087
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $585
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $586
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1089
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1090
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$81 [1]
-    connect \B \fu_enable [1]
-    connect \Y $585
+    connect \A \wr_pick$1061
+    connect \B $1087
+    connect \Y $1089
   end
-  process $group_272
-    assign \wrpick_CR_full_cr_i 1'0
-    assign \wrpick_CR_full_cr_i $585
+  process $group_382
+    assign \wr_pick_rise$857 1'0
+    assign \wr_pick_rise$857 $1089
     sync init
   end
-  process $group_273
-    assign \cr_full_wr__data_i 32'00000000000000000000000000000000
-    assign \cr_full_wr__data_i \fus_dest2_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $1091
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $1092
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest3_o$123
+    connect \B \fus_dest3_o$124
+    connect \Y $1091
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $587
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 4 $588
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sub $589
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $1093
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $1094
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_out
-    connect \Y $588
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest6_o
+    connect \B \fus_dest3_o$125
+    connect \Y $1093
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $590
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sshl $591
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 2 $1095
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1096
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $588
-    connect \Y $590
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A $1091
+    connect \B $1093
+    connect \Y $1095
   end
-  connect $587 $590
-  process $group_274
-    assign \cr_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-      case 1'1
-        assign \cr_wen $587 [7:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \cr_wen 8'00000000
-    end
+  process $group_383
+    assign \xer_data_i 2'00
+    assign \xer_data_i $1095
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_alu0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $592
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $593
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_alu0_xer_ov_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1097
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1098
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok
+    connect \A \fus_xer_ov_ok
     connect \B \fus_cu_busy_o
-    connect \Y $592
+    connect \Y $1097
   end
-  process $group_275
-    assign \wrflag_alu0_cr_a_1 1'0
-    assign \wrflag_alu0_cr_a_1 $592
+  process $group_384
+    assign \wrflag_alu0_xer_ov_3 1'0
+    assign \wrflag_alu0_xer_ov_3 $1097
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $594
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $595
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1099
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [1]
+    connect \A \fus_cu_wr__rel_o [3]
     connect \B \fu_enable [0]
-    connect \Y $594
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $596
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $597
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$81 [2]
-    connect \B \fu_enable [1]
-    connect \Y $596
+    connect \Y $1099
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $598
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $599
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$87 [1]
-    connect \B \fu_enable [4]
-    connect \Y $598
+    connect \A \fus_cu_wr__rel_o$90 [4]
+    connect \B \fu_enable [5]
+    connect \Y $1101
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $600
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $601
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$93 [1]
+    connect \A \fus_cu_wr__rel_o$93 [2]
     connect \B \fu_enable [6]
-    connect \Y $600
+    connect \Y $1103
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $602
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $603
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$96 [1]
+    connect \A \fus_cu_wr__rel_o$96 [2]
     connect \B \fu_enable [7]
-    connect \Y $602
+    connect \Y $1105
+  end
+  process $group_385
+    assign \wrpick_XER_xer_ov_i 4'0000
+    assign \wrpick_XER_xer_ov_i [0] $1099
+    assign \wrpick_XER_xer_ov_i [1] $1101
+    assign \wrpick_XER_xer_ov_i [2] $1103
+    assign \wrpick_XER_xer_ov_i [3] $1105
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $604
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $605
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$99 [1]
-    connect \B \fu_enable [8]
-    connect \Y $604
+    connect \A \wrpick_XER_xer_ov_o [0]
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1108
   end
-  process $group_276
-    assign \wrpick_CR_cr_a_i 6'000000
-    assign \wrpick_CR_cr_a_i [0] $594
-    assign \wrpick_CR_cr_a_i [1] $596
-    assign \wrpick_CR_cr_a_i [2] $598
-    assign \wrpick_CR_cr_a_i [3] $600
-    assign \wrpick_CR_cr_a_i [4] $602
-    assign \wrpick_CR_cr_a_i [5] $604
+  process $group_386
+    assign \wr_pick$1107 1'0
+    assign \wr_pick$1107 $1108
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_cr0_cr_a_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $606
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $607
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1110
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1110$next
+  process $group_387
+    assign \wr_pick_dly$1110$next \wr_pick_dly$1110
+    assign \wr_pick_dly$1110$next \wr_pick$1107
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1110$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1110 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1110 \wr_pick_dly$1110$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1111
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$110
-    connect \B \fus_cu_busy_o$4
-    connect \Y $606
-  end
-  process $group_277
-    assign \wrflag_cr0_cr_a_2 1'0
-    assign \wrflag_cr0_cr_a_2 $606
-    sync init
+    connect \A \wr_pick_dly$1110
+    connect \Y $1111
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_logical0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $608
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $609
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1113
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$111
-    connect \B \fus_cu_busy_o$13
-    connect \Y $608
+    connect \A \wr_pick$1107
+    connect \B $1111
+    connect \Y $1113
   end
-  process $group_278
-    assign \wrflag_logical0_cr_a_1 1'0
-    assign \wrflag_logical0_cr_a_1 $608
+  process $group_388
+    assign \wr_pick_rise$716 1'0
+    assign \wr_pick_rise$716 $1113
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_div0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $610
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $611
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1115
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$112
-    connect \B \fus_cu_busy_o$19
-    connect \Y $610
-  end
-  process $group_279
-    assign \wrflag_div0_cr_a_1 1'0
-    assign \wrflag_div0_cr_a_1 $610
-    sync init
+    connect \A \wr_pick$1107
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_mul0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $612
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $613
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1117
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1118
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$113
-    connect \B \fus_cu_busy_o$22
-    connect \Y $612
-  end
-  process $group_280
-    assign \wrflag_mul0_cr_a_1 1'0
-    assign \wrflag_mul0_cr_a_1 $612
-    sync init
+    connect \A \wr_pick$1117
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1118
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_shiftrot0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $614
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $615
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1120
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1121
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$114
-    connect \B \fus_cu_busy_o$25
-    connect \Y $614
-  end
-  process $group_281
-    assign \wrflag_shiftrot0_cr_a_1 1'0
-    assign \wrflag_shiftrot0_cr_a_1 $614
-    sync init
+    connect \A \wr_pick$1120
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1121
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $616
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $617
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1123
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1125
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest3_o
-    connect \B \fus_dest2_o$116
-    connect \Y $616
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1123
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1124
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $618
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $619
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$115
-    connect \B $616
-    connect \Y $618
+  process $group_389
+    assign \xer_wen$153 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1115 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$153 3'100
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1118 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$153 3'100
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1121 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$153 3'100
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1124 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$153 3'100
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $620
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $621
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_spr0_xer_ov_4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1126
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1127
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$118
-    connect \B \fus_dest2_o$119
-    connect \Y $620
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_xer_ov_ok$126
+    connect \B \fus_cu_busy_o$16
+    connect \Y $1126
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $622
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $623
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$117
-    connect \B $620
-    connect \Y $622
+  process $group_390
+    assign \wrflag_spr0_xer_ov_4 1'0
+    assign \wrflag_spr0_xer_ov_4 $1126
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $624
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $625
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1128
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1129
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $618
-    connect \B $622
-    connect \Y $624
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_XER_xer_ov_o [1]
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1128
   end
-  process $group_282
-    assign \cr_data_i 4'0000
-    assign \cr_data_i $624
+  process $group_391
+    assign \wr_pick$1117 1'0
+    assign \wr_pick$1117 $1128
     sync init
   end
-  process $group_283
-    assign \xer_wen 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_XER_xer_ca_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1130
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1130$next
+  process $group_392
+    assign \wr_pick_dly$1130$next \wr_pick_dly$1130
+    assign \wr_pick_dly$1130$next \wr_pick$1117
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \xer_wen 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \xer_wen 3'000
+        assign \wr_pick_dly$1130$next 1'0
     end
     sync init
+      update \wr_pick_dly$1130 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1130 \wr_pick_dly$1130$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_alu0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $626
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $627
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1131
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1132
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1130
+    connect \Y $1131
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1133
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $626
+    connect \A \wr_pick$1117
+    connect \B $1131
+    connect \Y $1133
   end
-  process $group_284
-    assign \wrflag_alu0_xer_ca_2 1'0
-    assign \wrflag_alu0_xer_ca_2 $626
+  process $group_393
+    assign \wr_pick_rise$816 1'0
+    assign \wr_pick_rise$816 $1133
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $628
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $629
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_div0_xer_ov_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [2]
-    connect \B \fu_enable [0]
-    connect \Y $628
+    connect \A \fus_xer_ov_ok$127
+    connect \B \fus_cu_busy_o$19
+    connect \Y $1135
+  end
+  process $group_394
+    assign \wrflag_div0_xer_ov_2 1'0
+    assign \wrflag_div0_xer_ov_2 $1135
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $630
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $631
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1137
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$87 [2]
-    connect \B \fu_enable [4]
-    connect \Y $630
+    connect \A \wrpick_XER_xer_ov_o [2]
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1137
+  end
+  process $group_395
+    assign \wr_pick$1120 1'0
+    assign \wr_pick$1120 $1137
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1139
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1139$next
+  process $group_396
+    assign \wr_pick_dly$1139$next \wr_pick_dly$1139
+    assign \wr_pick_dly$1139$next \wr_pick$1120
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1139$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1139 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1139 \wr_pick_dly$1139$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $632
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $633
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1140
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [5]
-    connect \B \fu_enable [5]
-    connect \Y $632
+    connect \A \wr_pick_dly$1139
+    connect \Y $1140
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $634
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $635
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1142
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$99 [2]
-    connect \B \fu_enable [8]
-    connect \Y $634
+    connect \A \wr_pick$1120
+    connect \B $1140
+    connect \Y $1142
   end
-  process $group_285
-    assign \wrpick_XER_xer_ca_i 4'0000
-    assign \wrpick_XER_xer_ca_i [0] $628
-    assign \wrpick_XER_xer_ca_i [1] $630
-    assign \wrpick_XER_xer_ca_i [2] $632
-    assign \wrpick_XER_xer_ca_i [3] $634
+  process $group_397
+    assign \wr_pick_rise$831 1'0
+    assign \wr_pick_rise$831 $1142
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_logical0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $636
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $637
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_mul0_xer_ov_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1144
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$120
-    connect \B \fus_cu_busy_o$13
-    connect \Y $636
+    connect \A \fus_xer_ov_ok$128
+    connect \B \fus_cu_busy_o$22
+    connect \Y $1144
   end
-  process $group_286
-    assign \wrflag_logical0_xer_ca_2 1'0
-    assign \wrflag_logical0_xer_ca_2 $636
+  process $group_398
+    assign \wrflag_mul0_xer_ov_2 1'0
+    assign \wrflag_mul0_xer_ov_2 $1144
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_spr0_xer_ca_5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $638
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $639
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$121
-    connect \B \fus_cu_busy_o$16
-    connect \Y $638
+    connect \A \wrpick_XER_xer_ov_o [3]
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $1146
   end
-  process $group_287
-    assign \wrflag_spr0_xer_ca_5 1'0
-    assign \wrflag_spr0_xer_ca_5 $638
+  process $group_399
+    assign \wr_pick$1123 1'0
+    assign \wr_pick$1123 $1146
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_shiftrot0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $640
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $641
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1148
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1148$next
+  process $group_400
+    assign \wr_pick_dly$1148$next \wr_pick_dly$1148
+    assign \wr_pick_dly$1148$next \wr_pick$1123
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1148$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1148 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1148 \wr_pick_dly$1148$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1149
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1150
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1148
+    connect \Y $1149
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1151
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$122
-    connect \B \fus_cu_busy_o$25
-    connect \Y $640
+    connect \A \wr_pick$1123
+    connect \B $1149
+    connect \Y $1151
   end
-  process $group_288
-    assign \wrflag_shiftrot0_xer_ca_2 1'0
-    assign \wrflag_shiftrot0_xer_ca_2 $640
+  process $group_401
+    assign \wr_pick_rise$844 1'0
+    assign \wr_pick_rise$844 $1151
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $642
+  wire width 2 $1153
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $643
+  cell $or $1154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \fus_dest3_o$123
-    connect \B \fus_dest3_o$124
-    connect \Y $642
+    connect \A \fus_dest4_o
+    connect \B \fus_dest5_o
+    connect \Y $1153
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $644
+  wire width 2 $1155
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $645
+  cell $or $1156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \fus_dest6_o
-    connect \B \fus_dest3_o$125
-    connect \Y $644
+    connect \A \fus_dest3_o$129
+    connect \B \fus_dest3_o$130
+    connect \Y $1155
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $646
+  wire width 2 $1157
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $647
+  cell $or $1158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A $642
-    connect \B $644
-    connect \Y $646
-  end
-  process $group_289
-    assign \xer_data_i 2'00
-    assign \xer_data_i $646
-    sync init
+    connect \A $1153
+    connect \B $1155
+    connect \Y $1157
   end
-  process $group_290
-    assign \xer_wen$155 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-      case 1'1
-        assign \xer_wen$155 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \xer_wen$155 3'000
-    end
+  process $group_402
+    assign \xer_data_i$154 2'00
+    assign \xer_data_i$154 $1157
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_alu0_xer_ov_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $648
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $649
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_alu0_xer_so_4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1159
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok
+    connect \A \fus_xer_so_ok
     connect \B \fus_cu_busy_o
-    connect \Y $648
+    connect \Y $1159
   end
-  process $group_291
-    assign \wrflag_alu0_xer_ov_3 1'0
-    assign \wrflag_alu0_xer_ov_3 $648
+  process $group_403
+    assign \wrflag_alu0_xer_so_4 1'0
+    assign \wrflag_alu0_xer_so_4 $1159
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $650
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $651
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1161
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [3]
+    connect \A \fus_cu_wr__rel_o [4]
     connect \B \fu_enable [0]
-    connect \Y $650
+    connect \Y $1161
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $652
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $653
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1163
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [4]
+    connect \A \fus_cu_wr__rel_o$90 [3]
     connect \B \fu_enable [5]
-    connect \Y $652
+    connect \Y $1163
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $654
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $655
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1165
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$93 [2]
+    connect \A \fus_cu_wr__rel_o$93 [3]
     connect \B \fu_enable [6]
-    connect \Y $654
+    connect \Y $1165
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $656
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $657
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1167
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$96 [2]
+    connect \A \fus_cu_wr__rel_o$96 [3]
     connect \B \fu_enable [7]
-    connect \Y $656
+    connect \Y $1167
   end
-  process $group_292
-    assign \wrpick_XER_xer_ov_i 4'0000
-    assign \wrpick_XER_xer_ov_i [0] $650
-    assign \wrpick_XER_xer_ov_i [1] $652
-    assign \wrpick_XER_xer_ov_i [2] $654
-    assign \wrpick_XER_xer_ov_i [3] $656
+  process $group_404
+    assign \wrpick_XER_xer_so_i 4'0000
+    assign \wrpick_XER_xer_so_i [0] $1161
+    assign \wrpick_XER_xer_so_i [1] $1163
+    assign \wrpick_XER_xer_so_i [2] $1165
+    assign \wrpick_XER_xer_so_i [3] $1167
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_spr0_xer_ov_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $658
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $659
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1169
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1170
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$126
-    connect \B \fus_cu_busy_o$16
-    connect \Y $658
+    connect \A \wrpick_XER_xer_so_o [0]
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1170
   end
-  process $group_293
-    assign \wrflag_spr0_xer_ov_4 1'0
-    assign \wrflag_spr0_xer_ov_4 $658
+  process $group_405
+    assign \wr_pick$1169 1'0
+    assign \wr_pick$1169 $1170
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_div0_xer_ov_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $660
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $661
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1172
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1172$next
+  process $group_406
+    assign \wr_pick_dly$1172$next \wr_pick_dly$1172
+    assign \wr_pick_dly$1172$next \wr_pick$1169
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1172$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1172 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1172 \wr_pick_dly$1172$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1173
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1174
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1172
+    connect \Y $1173
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1175
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$127
-    connect \B \fus_cu_busy_o$19
-    connect \Y $660
+    connect \A \wr_pick$1169
+    connect \B $1173
+    connect \Y $1175
   end
-  process $group_294
-    assign \wrflag_div0_xer_ov_2 1'0
-    assign \wrflag_div0_xer_ov_2 $660
+  process $group_407
+    assign \wr_pick_rise$717 1'0
+    assign \wr_pick_rise$717 $1175
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_mul0_xer_ov_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $662
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $663
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1177
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1178
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$128
-    connect \B \fus_cu_busy_o$22
-    connect \Y $662
-  end
-  process $group_295
-    assign \wrflag_mul0_xer_ov_2 1'0
-    assign \wrflag_mul0_xer_ov_2 $662
-    sync init
+    connect \A \wr_pick$1169
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1177
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $664
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $665
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1179
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1180
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1181
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest4_o
-    connect \B \fus_dest5_o
-    connect \Y $664
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1179
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1180
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $666
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $667
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1182
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1183
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1184
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest3_o$129
-    connect \B \fus_dest3_o$130
-    connect \Y $666
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1182
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1183
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $668
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $669
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1185
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1186
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1187
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A $664
-    connect \B $666
-    connect \Y $668
-  end
-  process $group_296
-    assign \xer_data_i$156 2'00
-    assign \xer_data_i$156 $668
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1185
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1186
   end
-  process $group_297
-    assign \xer_wen$157 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_XER_xer_so_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  process $group_408
+    assign \xer_wen$155 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1177 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
       case 1'1
-        assign \xer_wen$157 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \xer_wen$157 3'000
+        assign \xer_wen$155 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1180 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$155 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1183 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$155 3'001
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1186 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \xer_wen$155 3'001
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_alu0_xer_so_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $670
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $671
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_spr0_xer_so_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1188
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1189
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $670
+    connect \A \fus_xer_so_ok$131
+    connect \B \fus_cu_busy_o$16
+    connect \Y $1188
   end
-  process $group_298
-    assign \wrflag_alu0_xer_so_4 1'0
-    assign \wrflag_alu0_xer_so_4 $670
+  process $group_409
+    assign \wrflag_spr0_xer_so_3 1'0
+    assign \wrflag_spr0_xer_so_3 $1188
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $672
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $673
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1190
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [4]
-    connect \B \fu_enable [0]
-    connect \Y $672
+    connect \A \wrpick_XER_xer_so_o [1]
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1190
+  end
+  process $group_410
+    assign \wr_pick$1179 1'0
+    assign \wr_pick$1179 $1190
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1192
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1192$next
+  process $group_411
+    assign \wr_pick_dly$1192$next \wr_pick_dly$1192
+    assign \wr_pick_dly$1192$next \wr_pick$1179
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1192$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1192 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1192 \wr_pick_dly$1192$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $674
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $675
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1193
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1194
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [3]
-    connect \B \fu_enable [5]
-    connect \Y $674
+    connect \A \wr_pick_dly$1192
+    connect \Y $1193
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $676
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $677
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1195
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$93 [3]
-    connect \B \fu_enable [6]
-    connect \Y $676
+    connect \A \wr_pick$1179
+    connect \B $1193
+    connect \Y $1195
+  end
+  process $group_412
+    assign \wr_pick_rise$817 1'0
+    assign \wr_pick_rise$817 $1195
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $678
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $679
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_div0_xer_so_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1197
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1198
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$96 [3]
-    connect \B \fu_enable [7]
-    connect \Y $678
+    connect \A \fus_xer_so_ok$132
+    connect \B \fus_cu_busy_o$19
+    connect \Y $1197
   end
-  process $group_299
-    assign \wrpick_XER_xer_so_i 4'0000
-    assign \wrpick_XER_xer_so_i [0] $672
-    assign \wrpick_XER_xer_so_i [1] $674
-    assign \wrpick_XER_xer_so_i [2] $676
-    assign \wrpick_XER_xer_so_i [3] $678
+  process $group_413
+    assign \wrflag_div0_xer_so_3 1'0
+    assign \wrflag_div0_xer_so_3 $1197
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_spr0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $680
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $681
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1199
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$131
-    connect \B \fus_cu_busy_o$16
-    connect \Y $680
+    connect \A \wrpick_XER_xer_so_o [2]
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1199
   end
-  process $group_300
-    assign \wrflag_spr0_xer_so_3 1'0
-    assign \wrflag_spr0_xer_so_3 $680
+  process $group_414
+    assign \wr_pick$1182 1'0
+    assign \wr_pick$1182 $1199
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_div0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $682
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $683
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1201
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1201$next
+  process $group_415
+    assign \wr_pick_dly$1201$next \wr_pick_dly$1201
+    assign \wr_pick_dly$1201$next \wr_pick$1182
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1201$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1201 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1201 \wr_pick_dly$1201$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1202
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1203
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1201
+    connect \Y $1202
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1204
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1205
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$132
-    connect \B \fus_cu_busy_o$19
-    connect \Y $682
+    connect \A \wr_pick$1182
+    connect \B $1202
+    connect \Y $1204
   end
-  process $group_301
-    assign \wrflag_div0_xer_so_3 1'0
-    assign \wrflag_div0_xer_so_3 $682
+  process $group_416
+    assign \wr_pick_rise$832 1'0
+    assign \wr_pick_rise$832 $1204
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_mul0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $684
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $685
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1206
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173492,19 +166557,82 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_xer_so_ok$133
     connect \B \fus_cu_busy_o$22
-    connect \Y $684
+    connect \Y $1206
   end
-  process $group_302
+  process $group_417
     assign \wrflag_mul0_xer_so_3 1'0
-    assign \wrflag_mul0_xer_so_3 $684
+    assign \wrflag_mul0_xer_so_3 $1206
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1208
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1209
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_XER_xer_so_o [3]
+    connect \B \wrpick_XER_xer_so_en_o
+    connect \Y $1208
+  end
+  process $group_418
+    assign \wr_pick$1185 1'0
+    assign \wr_pick$1185 $1208
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1210
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1210$next
+  process $group_419
+    assign \wr_pick_dly$1210$next \wr_pick_dly$1210
+    assign \wr_pick_dly$1210$next \wr_pick$1185
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1210$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1210 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1210 \wr_pick_dly$1210$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1211
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1212
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1210
+    connect \Y $1211
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1213
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1214
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1185
+    connect \B $1211
+    connect \Y $1213
+  end
+  process $group_420
+    assign \wr_pick_rise$845 1'0
+    assign \wr_pick_rise$845 $1213
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $686
+  wire width 2 $1215
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 1 $687
+  wire width 1 $1216
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $688
+  cell $or $1217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173512,12 +166640,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_dest5_o$134
     connect \B \fus_dest4_o$135
-    connect \Y $687
+    connect \Y $1216
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 1 $689
+  wire width 1 $1218
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $690
+  cell $or $1219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173525,66 +166653,40 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_dest4_o$136
     connect \B \fus_dest4_o$137
-    connect \Y $689
+    connect \Y $1218
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 1 $691
+  wire width 1 $1220
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $692
+  cell $or $1221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $687
-    connect \B $689
-    connect \Y $691
+    connect \A $1216
+    connect \B $1218
+    connect \Y $1220
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $pos $693
+  cell $pos $1222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 2
-    connect \A $691
-    connect \Y $686
-  end
-  process $group_303
-    assign \xer_data_i$158 2'00
-    assign \xer_data_i$158 $686
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  wire width 8 $694
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  cell $sshl $695
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fasto1
-    connect \Y $694
+    connect \A $1220
+    connect \Y $1215
   end
-  process $group_304
-    assign \fast_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-      case 1'1
-        assign \fast_wen $694
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \fast_wen 8'00000000
-    end
+  process $group_421
+    assign \xer_data_i$156 2'00
+    assign \xer_data_i$156 $1215
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_branch0_fast1_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $696
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $697
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173592,17 +166694,17 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_fast1_ok
     connect \B \fus_cu_busy_o$7
-    connect \Y $696
+    connect \Y $1223
   end
-  process $group_305
+  process $group_422
     assign \wrflag_branch0_fast1_0 1'0
-    assign \wrflag_branch0_fast1_0 $696
+    assign \wrflag_branch0_fast1_0 $1223
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $698
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $699
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1225
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1226
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173610,12 +166712,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$138 [0]
     connect \B \fu_enable [2]
-    connect \Y $698
+    connect \Y $1225
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $700
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $701
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1227
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1228
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173623,12 +166725,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$84 [1]
     connect \B \fu_enable [3]
-    connect \Y $700
+    connect \Y $1227
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $702
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $703
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1229
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173636,19 +166738,49 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$90 [2]
     connect \B \fu_enable [5]
-    connect \Y $702
+    connect \Y $1229
   end
-  process $group_306
-    assign \wrpick_FAST_fast1_i 3'000
-    assign \wrpick_FAST_fast1_i [0] $698
-    assign \wrpick_FAST_fast1_i [1] $700
-    assign \wrpick_FAST_fast1_i [2] $702
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1231
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1232
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$138 [1]
+    connect \B \fu_enable [2]
+    connect \Y $1231
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1233
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1234
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$84 [2]
+    connect \B \fu_enable [3]
+    connect \Y $1233
+  end
+  process $group_423
+    assign \wrpick_FAST_fast1_i 5'00000
+    assign \wrpick_FAST_fast1_i [0] $1225
+    assign \wrpick_FAST_fast1_i [1] $1227
+    assign \wrpick_FAST_fast1_i [2] $1229
+    assign \wrpick_FAST_fast1_i [3] $1231
+    assign \wrpick_FAST_fast1_i [4] $1233
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $704
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $705
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1235
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1236
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173656,47 +166788,264 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [0]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $704
+    connect \Y $1236
+  end
+  process $group_424
+    assign \wr_pick$1235 1'0
+    assign \wr_pick$1235 $1236
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1238
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1238$next
+  process $group_425
+    assign \wr_pick_dly$1238$next \wr_pick_dly$1238
+    assign \wr_pick_dly$1238$next \wr_pick$1235
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1238$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1238 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1238 \wr_pick_dly$1238$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$1239
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1240
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1241
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1238
+    connect \Y $1240
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $706
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $707
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1242
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast2_o [0]
-    connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $706
+    connect \A \wr_pick$1235
+    connect \B $1240
+    connect \Y $1242
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  wire width 1 $708
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
-  cell $and $709
+  process $group_426
+    assign \wr_pick_rise$1239 1'0
+    assign \wr_pick_rise$1239 $1242
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$1244
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \wr_pick_rise$1245
+  process $group_427
+    assign \fus_cu_wr__go_i$139 3'000
+    assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1239
+    assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1244
+    assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1245
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1246
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1247
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_nia_o [0]
-    connect \B \wrpick_FAST_nia_en_o
-    connect \Y $708
+    connect \A \wr_pick$1235
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1246
   end
-  process $group_307
-    assign \fus_cu_wr__go_i$139 3'000
-    assign \fus_cu_wr__go_i$139 [0] $704
-    assign \fus_cu_wr__go_i$139 [1] $706
-    assign \fus_cu_wr__go_i$139 [2] $708
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1248
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1249
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  cell $sshl $1250
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto1
+    connect \Y $1249
+  end
+  connect $1248 $1249
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1251
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1252
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1253
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1251
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1252
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1254
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1255
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  cell $sshl $1256
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto1
+    connect \Y $1255
+  end
+  connect $1254 $1255
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1257
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1258
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1259
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1257
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1258
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1260
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  wire width 8 $1261
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178"
+  cell $sshl $1262
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto1
+    connect \Y $1261
+  end
+  connect $1260 $1261
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1263
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1264
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1265
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1263
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1264
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  wire width 8 $1266
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  wire width 8 $1267
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  cell $sshl $1268
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto2
+    connect \Y $1267
+  end
+  connect $1266 $1267
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1269
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1270
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1271
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1269
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1270
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  wire width 8 $1272
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  wire width 8 $1273
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180"
+  cell $sshl $1274
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto2
+    connect \Y $1273
+  end
+  connect $1272 $1273
+  process $group_428
+    assign \fast_wen 5'00000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1246 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \fast_wen $1248 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1252 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \fast_wen $1254 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1258 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \fast_wen $1260 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1264 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \fast_wen $1266 [4:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1270 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \fast_wen $1272 [4:0]
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_trap0_fast1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $710
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $711
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1275
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173704,19 +167053,82 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_fast1_ok$140
     connect \B \fus_cu_busy_o$10
-    connect \Y $710
+    connect \Y $1275
   end
-  process $group_308
+  process $group_429
     assign \wrflag_trap0_fast1_1 1'0
-    assign \wrflag_trap0_fast1_1 $710
+    assign \wrflag_trap0_fast1_1 $1275
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1277
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1278
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_FAST_fast1_o [1]
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1277
+  end
+  process $group_430
+    assign \wr_pick$1251 1'0
+    assign \wr_pick$1251 $1277
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1279
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1279$next
+  process $group_431
+    assign \wr_pick_dly$1279$next \wr_pick_dly$1279
+    assign \wr_pick_dly$1279$next \wr_pick$1251
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1279$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1279 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1279 \wr_pick_dly$1279$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1280
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1281
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1279
+    connect \Y $1280
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1282
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1283
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1251
+    connect \B $1280
+    connect \Y $1282
+  end
+  process $group_432
+    assign \wr_pick_rise$789 1'0
+    assign \wr_pick_rise$789 $1282
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_spr0_fast1_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $712
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $713
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1284
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173724,146 +167136,259 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_fast1_ok$141
     connect \B \fus_cu_busy_o$16
-    connect \Y $712
+    connect \Y $1284
   end
-  process $group_309
+  process $group_433
     assign \wrflag_spr0_fast1_2 1'0
-    assign \wrflag_spr0_fast1_2 $712
+    assign \wrflag_spr0_fast1_2 $1284
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $714
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $715
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1286
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1287
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$143
-    connect \B \fus_dest3_o$144
-    connect \Y $714
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_FAST_fast1_o [2]
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1286
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $716
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $717
+  process $group_434
+    assign \wr_pick$1257 1'0
+    assign \wr_pick$1257 $1286
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1288
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1288$next
+  process $group_435
+    assign \wr_pick_dly$1288$next \wr_pick_dly$1288
+    assign \wr_pick_dly$1288$next \wr_pick$1257
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1288$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1288 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1288 \wr_pick_dly$1288$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1289
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1290
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1288
+    connect \Y $1289
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1291
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1292
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$142
-    connect \B $714
-    connect \Y $716
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1257
+    connect \B $1289
+    connect \Y $1291
   end
-  process $group_310
-    assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i $716
+  process $group_436
+    assign \wr_pick_rise$818 1'0
+    assign \wr_pick_rise$818 $1291
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  wire width 8 $718
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  cell $sshl $719
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_branch0_fast1_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1293
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fasto2
-    connect \Y $718
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_fast2_ok
+    connect \B \fus_cu_busy_o$7
+    connect \Y $1293
   end
-  process $group_311
-    assign \fast_wen$159 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  process $group_437
+    assign \wrflag_branch0_fast1_1 1'0
+    assign \wrflag_branch0_fast1_1 $1293
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1295
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1296
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_FAST_fast1_o [3]
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1295
+  end
+  process $group_438
+    assign \wr_pick$1263 1'0
+    assign \wr_pick$1263 $1295
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1297
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1297$next
+  process $group_439
+    assign \wr_pick_dly$1297$next \wr_pick_dly$1297
+    assign \wr_pick_dly$1297$next \wr_pick$1263
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \fast_wen$159 $718
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \fast_wen$159 8'00000000
+        assign \wr_pick_dly$1297$next 1'0
     end
     sync init
+      update \wr_pick_dly$1297 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1297 \wr_pick_dly$1297$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_branch0_fast2_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $720
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $721
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1298
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1299
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1297
+    connect \Y $1298
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1300
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok
-    connect \B \fus_cu_busy_o$7
-    connect \Y $720
+    connect \A \wr_pick$1263
+    connect \B $1298
+    connect \Y $1300
   end
-  process $group_312
-    assign \wrflag_branch0_fast2_1 1'0
-    assign \wrflag_branch0_fast2_1 $720
+  process $group_440
+    assign \wr_pick_rise$1244 1'0
+    assign \wr_pick_rise$1244 $1300
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $722
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $723
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
+  wire width 1 \wrflag_trap0_fast1_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1302
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$138 [1]
-    connect \B \fu_enable [2]
-    connect \Y $722
+    connect \A \fus_fast2_ok$142
+    connect \B \fus_cu_busy_o$10
+    connect \Y $1302
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $724
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $725
+  process $group_441
+    assign \wrflag_trap0_fast1_2 1'0
+    assign \wrflag_trap0_fast1_2 $1302
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1304
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$84 [2]
-    connect \B \fu_enable [3]
-    connect \Y $724
+    connect \A \wrpick_FAST_fast1_o [4]
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $1304
   end
-  process $group_313
-    assign \wrpick_FAST_fast2_i 2'00
-    assign \wrpick_FAST_fast2_i [0] $722
-    assign \wrpick_FAST_fast2_i [1] $724
+  process $group_442
+    assign \wr_pick$1269 1'0
+    assign \wr_pick$1269 $1304
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
-  wire width 1 \wrflag_trap0_fast2_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $726
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $727
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1306
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1306$next
+  process $group_443
+    assign \wr_pick_dly$1306$next \wr_pick_dly$1306
+    assign \wr_pick_dly$1306$next \wr_pick$1269
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1306$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1306 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1306 \wr_pick_dly$1306$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1307
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1308
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1306
+    connect \Y $1307
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1309
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok$145
-    connect \B \fus_cu_busy_o$10
-    connect \Y $726
+    connect \A \wr_pick$1269
+    connect \B $1307
+    connect \Y $1309
   end
-  process $group_314
-    assign \wrflag_trap0_fast2_2 1'0
-    assign \wrflag_trap0_fast2_2 $726
+  process $group_444
+    assign \wr_pick_rise$790 1'0
+    assign \wr_pick_rise$790 $1309
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $728
+  wire width 64 $1311
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $1312
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$143
+    connect \B \fus_dest2_o$144
+    connect \Y $1311
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $1313
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $729
+  cell $or $1314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -173871,32 +167396,45 @@ module \core
     parameter \Y_WIDTH 64
     connect \A \fus_dest2_o$146
     connect \B \fus_dest3_o$147
-    connect \Y $728
+    connect \Y $1313
   end
-  process $group_315
-    assign \fast_data_i$160 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$160 $728
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $1315
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1316
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest3_o$145
+    connect \B $1313
+    connect \Y $1315
   end
-  process $group_316
-    assign \fast_nia_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_FAST_nia_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-      case 1'1
-        assign \fast_nia_wen 8'00000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \fast_nia_wen 8'00000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $1317
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $1318
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $1311
+    connect \B $1315
+    connect \Y $1317
+  end
+  process $group_445
+    assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i $1317
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_branch0_nia_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $730
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $731
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1319
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173904,17 +167442,17 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_nia_ok
     connect \B \fus_cu_busy_o$7
-    connect \Y $730
+    connect \Y $1319
   end
-  process $group_317
+  process $group_446
     assign \wrflag_branch0_nia_2 1'0
-    assign \wrflag_branch0_nia_2 $730
+    assign \wrflag_branch0_nia_2 $1319
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $732
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $733
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1321
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173922,12 +167460,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$138 [2]
     connect \B \fu_enable [2]
-    connect \Y $732
+    connect \Y $1321
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $734
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $735
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1323
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173935,20 +167473,129 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$84 [3]
     connect \B \fu_enable [3]
-    connect \Y $734
+    connect \Y $1323
   end
-  process $group_318
-    assign \wrpick_FAST_nia_i 2'00
-    assign \wrpick_FAST_nia_i [0] $732
-    assign \wrpick_FAST_nia_i [1] $734
+  process $group_447
+    assign \wrpick_STATE_nia_i 2'00
+    assign \wrpick_STATE_nia_i [0] $1321
+    assign \wrpick_STATE_nia_i [1] $1323
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1325
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1326
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1327
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_STATE_nia_o [0]
+    connect \B \wrpick_STATE_nia_en_o
+    connect \Y $1326
+  end
+  process $group_448
+    assign \wr_pick$1325 1'0
+    assign \wr_pick$1325 $1326
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1328
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1328$next
+  process $group_449
+    assign \wr_pick_dly$1328$next \wr_pick_dly$1328
+    assign \wr_pick_dly$1328$next \wr_pick$1325
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1328$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1328 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1328 \wr_pick_dly$1328$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1329
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1330
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1328
+    connect \Y $1329
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1331
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1332
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1325
+    connect \B $1329
+    connect \Y $1331
+  end
+  process $group_450
+    assign \wr_pick_rise$1245 1'0
+    assign \wr_pick_rise$1245 $1331
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1333
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1334
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1325
+    connect \B \wrpick_STATE_nia_en_o
+    connect \Y $1333
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1335
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1336
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1337
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1335
+    connect \B \wrpick_STATE_nia_en_o
+    connect \Y $1336
+  end
+  process $group_451
+    assign \state_nia_wen 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1333 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \state_nia_wen 2'01
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1336 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \state_nia_wen 2'01
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_trap0_nia_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $736
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $737
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1338
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -173956,17 +167603,80 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_nia_ok$148
     connect \B \fus_cu_busy_o$10
-    connect \Y $736
+    connect \Y $1338
   end
-  process $group_319
+  process $group_452
     assign \wrflag_trap0_nia_3 1'0
-    assign \wrflag_trap0_nia_3 $736
+    assign \wrflag_trap0_nia_3 $1338
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1340
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1341
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_STATE_nia_o [1]
+    connect \B \wrpick_STATE_nia_en_o
+    connect \Y $1340
+  end
+  process $group_453
+    assign \wr_pick$1335 1'0
+    assign \wr_pick$1335 $1340
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1342
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1342$next
+  process $group_454
+    assign \wr_pick_dly$1342$next \wr_pick_dly$1342
+    assign \wr_pick_dly$1342$next \wr_pick$1335
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1342$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1342 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1342 \wr_pick_dly$1342$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1343
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1344
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1342
+    connect \Y $1343
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1345
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1346
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1335
+    connect \B $1343
+    connect \Y $1345
+  end
+  process $group_455
+    assign \wr_pick_rise$791 1'0
+    assign \wr_pick_rise$791 $1345
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $738
+  wire width 64 $1347
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $739
+  cell $or $1348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -173974,32 +167684,19 @@ module \core
     parameter \Y_WIDTH 64
     connect \A \fus_dest3_o$149
     connect \B \fus_dest4_o$150
-    connect \Y $738
+    connect \Y $1347
   end
-  process $group_320
-    assign \fast_data_i$161 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$161 $738
-    sync init
-  end
-  process $group_321
-    assign \fast_wen$162 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_FAST_msr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-      case 1'1
-        assign \fast_wen$162 8'00000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \fast_wen$162 8'00000000
-    end
+  process $group_456
+    assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \state_data_i $1347
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_trap0_msr_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $740
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $741
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1349
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -174007,17 +167704,17 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_msr_ok
     connect \B \fus_cu_busy_o$10
-    connect \Y $740
+    connect \Y $1349
   end
-  process $group_322
+  process $group_457
     assign \wrflag_trap0_msr_4 1'0
-    assign \wrflag_trap0_msr_4 $740
+    assign \wrflag_trap0_msr_4 $1349
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $742
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $743
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1351
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -174025,37 +167722,112 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$84 [4]
     connect \B \fu_enable [3]
-    connect \Y $742
+    connect \Y $1351
   end
-  process $group_323
-    assign \wrpick_FAST_msr_i 1'0
-    assign \wrpick_FAST_msr_i $742
+  process $group_458
+    assign \wrpick_STATE_msr_i 1'0
+    assign \wrpick_STATE_msr_i $1351
     sync init
   end
-  process $group_324
-    assign \fast_data_i$163 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$163 \fus_dest5_o$151
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:327"
+  wire width 1 \wr_pick$1353
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1354
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1355
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_STATE_msr_o
+    connect \B \wrpick_STATE_msr_en_o
+    connect \Y $1354
+  end
+  process $group_459
+    assign \wr_pick$1353 1'0
+    assign \wr_pick$1353 $1354
     sync init
   end
-  process $group_325
-    assign \spr_dest__wen 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
-    switch { \wrpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1356
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1356$next
+  process $group_460
+    assign \wr_pick_dly$1356$next \wr_pick_dly$1356
+    assign \wr_pick_dly$1356$next \wr_pick$1353
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \spr_dest__wen \pdecode2_spro [0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
-      case
-        assign \spr_dest__wen 1'0
+        assign \wr_pick_dly$1356$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1356 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1356 \wr_pick_dly$1356$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1357
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1358
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1356
+    connect \Y $1357
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1359
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1360
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1353
+    connect \B $1357
+    connect \Y $1359
+  end
+  process $group_461
+    assign \wr_pick_rise$792 1'0
+    assign \wr_pick_rise$792 $1359
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  wire width 1 $1361
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+  cell $and $1362
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick$1353
+    connect \B \wrpick_STATE_msr_en_o
+    connect \Y $1361
+  end
+  process $group_462
+    assign \state_wen 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+    switch { $1361 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:334"
+      case 1'1
+        assign \state_wen 2'10
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  process $group_463
+    assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \state_data_i$157 \fus_dest5_o$151
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:319"
   wire width 1 \wrflag_spr0_spr1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  wire width 1 $744
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
-  cell $and $745
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  wire width 1 $1363
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:320"
+  cell $and $1364
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -174063,17 +167835,17 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_spr1_ok
     connect \B \fus_cu_busy_o$16
-    connect \Y $744
+    connect \Y $1363
   end
-  process $group_326
+  process $group_464
     assign \wrflag_spr0_spr1_1 1'0
-    assign \wrflag_spr0_spr1_1 $744
+    assign \wrflag_spr0_spr1_1 $1363
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $746
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $747
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  wire width 1 $1365
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:324"
+  cell $and $1366
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -174081,19 +167853,82 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \fus_cu_wr__rel_o$90 [1]
     connect \B \fu_enable [5]
-    connect \Y $746
+    connect \Y $1365
   end
-  process $group_327
+  process $group_465
     assign \wrpick_SPR_spr1_i 1'0
-    assign \wrpick_SPR_spr1_i $746
+    assign \wrpick_SPR_spr1_i $1365
     sync init
   end
-  process $group_328
-    assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \spr_dest__data_i \fus_dest2_o$152
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  wire width 1 $1367
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:328"
+  cell $and $1368
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wrpick_SPR_spr1_o
+    connect \B \wrpick_SPR_spr1_en_o
+    connect \Y $1367
+  end
+  process $group_466
+    assign \wr_pick 1'0
+    assign \wr_pick $1367
     sync init
   end
-  process $group_329
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1369
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \wr_pick_dly$1369$next
+  process $group_467
+    assign \wr_pick_dly$1369$next \wr_pick_dly$1369
+    assign \wr_pick_dly$1369$next \wr_pick
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wr_pick_dly$1369$next 1'0
+    end
+    sync init
+      update \wr_pick_dly$1369 1'0
+    sync posedge \coresync_clk
+      update \wr_pick_dly$1369 \wr_pick_dly$1369$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1370
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $1371
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick_dly$1369
+    connect \Y $1370
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $1372
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $1373
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_pick
+    connect \B $1370
+    connect \Y $1372
+  end
+  process $group_468
+    assign \wr_pick_rise$819 1'0
+    assign \wr_pick_rise$819 $1372
+    sync init
+  end
+  process $group_469
+    assign $memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign $memory_w_data \fus_dest2_o$152
+    sync init
+  end
+  process $group_470
     assign \coresync_rst 1'0
     assign \coresync_rst \core_reset_i
     sync init
@@ -174104,7 +167939,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.imem"
 module \imem
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 0 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
   wire width 48 input 1 \a_pc_i
@@ -174116,7 +167951,7 @@ module \imem
   wire width 1 output 4 \f_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
   wire width 64 output 5 \f_instr_o
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 6 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 output 7 \ibus__cyc
@@ -174663,7 +168498,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.dbg"
 module \dbg
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 0 \clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
   wire width 1 output 1 \core_stop_o
@@ -174683,7 +168518,7 @@ module \dbg
   wire width 64 input 8 \dbg_gpr_data
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67"
   wire width 1 input 9 \dbg_gpr_ack
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 10 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
   wire width 1 output 11 \dmi_ack_o
@@ -176019,17 +169854,17 @@ module \test_issuer
   wire width 64 input 0 \pc_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 1 \pc_i_ok
-  attribute \src "simple/issuer.py:54"
+  attribute \src "simple/issuer.py:56"
   wire width 64 output 2 \pc_o
-  attribute \src "simple/issuer.py:58"
+  attribute \src "simple/issuer.py:60"
   wire width 1 input 3 \memerr_o
-  attribute \src "simple/issuer.py:56"
+  attribute \src "simple/issuer.py:58"
   wire width 1 input 4 \core_bigendian_i
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 5 \clk
-  attribute \src "simple/issuer.py:86"
+  attribute \src "simple/issuer.py:88"
   wire width 1 input 6 \rst
-  attribute \src "simple/issuer.py:57"
+  attribute \src "simple/issuer.py:59"
   wire width 1 output 7 \busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55"
   wire width 4 input 8 \dmi_addr_i
@@ -176087,44 +169922,46 @@ module \test_issuer
   wire width 2 input 34 \dbus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 input 35 \dbus__err
-  attribute \src "simple/issuer.py:85"
-  wire width 1 \por_clk
   attribute \src "simple/issuer.py:87"
+  wire width 1 \por_clk
+  attribute \src "simple/issuer.py:89"
   wire width 1 \core_coresync_clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82"
   wire width 1 \core_corebusy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 \core_bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 \core_cu_st__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 1 \core_cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 1 \core_cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 1 \core_cu_st__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 \core_cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \core_cia__ren
+  wire width 2 \core_cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90"
   wire width 1 \core_core_reset_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91"
   wire width 1 \core_core_terminate_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \core_msr__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \core_msr__ren$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \core_msr__data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
   wire width 1 \core_valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:81"
   wire width 1 \core_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 \core_raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \core_msr__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \core_msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
-  wire width 64 \core_dec2_msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
   wire width 64 \core_dec2_pc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 \core_dec2_msr
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -176201,9 +170038,9 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
   wire width 7 \core_insn_type
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \core_fast_nia_wen
+  wire width 2 \core_state_nia_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \core_wen
+  wire width 2 \core_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -176214,23 +170051,23 @@ module \test_issuer
     connect \coresync_clk \core_coresync_clk
     connect \corebusy_o \core_corebusy_o
     connect \bigendian \core_bigendian
+    connect \cu_st__rel_o \core_cu_st__rel_o
     connect \cu_ad__go_i \core_cu_ad__go_i
     connect \cu_ad__rel_o \core_cu_ad__rel_o
     connect \cu_st__go_i \core_cu_st__go_i
-    connect \cu_st__rel_o \core_cu_st__rel_o
     connect \cia__ren \core_cia__ren
     connect \cia__data_o \core_cia__data_o
     connect \core_reset_i \core_core_reset_i
     connect \core_terminate_o \core_core_terminate_o
+    connect \msr__ren \core_msr__ren
+    connect \msr__data_o \core_msr__data_o
     connect \valid \core_valid
     connect \issue_i \core_issue_i
     connect \raw_opcode_in \core_raw_opcode_in
-    connect \msr__ren \core_msr__ren
-    connect \msr__data_o \core_msr__data_o
-    connect \dec2_msr \core_dec2_msr
     connect \dec2_pc \core_dec2_pc
+    connect \dec2_msr \core_dec2_msr
     connect \insn_type \core_insn_type
-    connect \fast_nia_wen \core_fast_nia_wen
+    connect \state_nia_wen \core_state_nia_wen
     connect \wen \core_wen
     connect \data_i \core_data_i
     connect \dmi__ren \core_dmi__ren
@@ -176239,9 +170076,9 @@ module \test_issuer
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
     connect \dbus__stb \dbus__stb
+    connect \dbus__sel \dbus__sel
     connect \dbus__dat_r \dbus__dat_r
     connect \dbus__adr \dbus__adr
-    connect \dbus__sel \dbus__sel
     connect \dbus__we \dbus__we
     connect \dbus__dat_w \dbus__dat_w
   end
@@ -176308,13 +170145,13 @@ module \test_issuer
     connect \dmi_we_i \dmi_we_i
     connect \dmi_din \dmi_din
   end
-  attribute \src "simple/issuer.py:90"
+  attribute \src "simple/issuer.py:92"
   wire width 2 \delay
-  attribute \src "simple/issuer.py:90"
+  attribute \src "simple/issuer.py:92"
   wire width 2 \delay$next
-  attribute \src "simple/issuer.py:91"
+  attribute \src "simple/issuer.py:93"
   wire width 1 $1
-  attribute \src "simple/issuer.py:91"
+  attribute \src "simple/issuer.py:93"
   cell $ne $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -176325,11 +170162,11 @@ module \test_issuer
     connect \B 1'0
     connect \Y $1
   end
-  attribute \src "simple/issuer.py:92"
+  attribute \src "simple/issuer.py:94"
   wire width 3 $3
-  attribute \src "simple/issuer.py:92"
+  attribute \src "simple/issuer.py:94"
   wire width 3 $4
-  attribute \src "simple/issuer.py:92"
+  attribute \src "simple/issuer.py:94"
   cell $sub $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -176343,9 +170180,9 @@ module \test_issuer
   connect $3 $4
   process $group_0
     assign \delay$next \delay
-    attribute \src "simple/issuer.py:91"
+    attribute \src "simple/issuer.py:93"
     switch { $1 }
-      attribute \src "simple/issuer.py:91"
+      attribute \src "simple/issuer.py:93"
       case 1'1
         assign \delay$next $3 [1:0]
     end
@@ -176374,21 +170211,63 @@ module \test_issuer
     assign \core_bigendian \core_bigendian_i
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \cu_st__rel_o_dly
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53"
+  wire width 1 \cu_st__rel_o_dly$next
   process $group_5
+    assign \cu_st__rel_o_dly$next \cu_st__rel_o_dly
+    assign \cu_st__rel_o_dly$next \core_cu_st__rel_o
+    sync init
+      update \cu_st__rel_o_dly 1'0
+    sync posedge \clk
+      update \cu_st__rel_o_dly \cu_st__rel_o_dly$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54"
+  wire width 1 \cu_st__rel_o_rise
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $not $7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \cu_st__rel_o_dly
+    connect \Y $6
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
+  cell $and $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \core_cu_st__rel_o
+    connect \B $6
+    connect \Y $8
+  end
+  process $group_6
+    assign \cu_st__rel_o_rise 1'0
+    assign \cu_st__rel_o_rise $8
+    sync init
+  end
+  process $group_7
     assign \core_cu_ad__go_i 1'0
     assign \core_cu_ad__go_i \core_cu_ad__rel_o
     sync init
   end
-  process $group_6
+  process $group_8
     assign \core_cu_st__go_i 1'0
-    assign \core_cu_st__go_i \core_cu_st__rel_o
+    assign \core_cu_st__go_i \cu_st__rel_o_rise
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
   wire width 64 \cur_pc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
   wire width 64 \cur_pc$next
-  process $group_7
+  process $group_9
     assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \pc_o \cur_pc
     sync init
@@ -176396,11 +170275,11 @@ module \test_issuer
   attribute \src "simple/issuer.py:121"
   wire width 64 \nia
   attribute \src "simple/issuer.py:122"
-  wire width 65 $6
+  wire width 65 $10
   attribute \src "simple/issuer.py:122"
-  wire width 65 $7
+  wire width 65 $11
   attribute \src "simple/issuer.py:122"
-  cell $add $8
+  cell $add $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -176408,17 +170287,17 @@ module \test_issuer
     parameter \Y_WIDTH 65
     connect \A \cur_pc
     connect \B 3'100
-    connect \Y $7
+    connect \Y $11
   end
-  connect $6 $7
-  process $group_8
+  connect $10 $11
+  process $group_10
     assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \nia $6 [63:0]
+    assign \nia $10 [63:0]
     sync init
   end
   attribute \src "simple/issuer.py:125"
   wire width 64 \pc
-  process $group_9
+  process $group_11
     assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:126"
     switch { \pc_i_ok }
@@ -176431,36 +170310,36 @@ module \test_issuer
     end
     sync init
   end
-  process $group_10
-    assign \core_cia__ren 8'00000000
+  process $group_12
+    assign \core_cia__ren 2'00
     attribute \src "simple/issuer.py:126"
     switch { \pc_i_ok }
       attribute \src "simple/issuer.py:126"
       case 1'1
       attribute \src "simple/issuer.py:129"
       case
-        assign \core_cia__ren 8'00000001
+        assign \core_cia__ren 2'01
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
   wire width 1 \core_stopped_i
-  process $group_11
+  process $group_13
     assign \core_stopped_i 1'0
     assign \core_stopped_i \dbg_core_stop_o
     sync init
   end
-  process $group_12
+  process $group_14
     assign \core_core_reset_i 1'0
     assign \core_core_reset_i \dbg_core_rst_o
     sync init
   end
-  process $group_13
+  process $group_15
     assign \dbg_terminate_i 1'0
     assign \dbg_terminate_i \core_core_terminate_o
     sync init
   end
-  process $group_14
+  process $group_16
     assign \dbg_core_dbg_pc 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \dbg_core_dbg_pc \pc
     sync init
@@ -176469,46 +170348,87 @@ module \test_issuer
   wire width 64 \cur_msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
   wire width 64 \cur_msr$next
-  process $group_15
+  process $group_17
     assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \dbg_core_dbg_msr \cur_msr
     sync init
   end
-  attribute \src "simple/issuer.py:113"
-  wire width 1 \pc_changed
-  attribute \src "simple/issuer.py:113"
-  wire width 1 \pc_changed$next
-  attribute \src "simple/issuer.py:157"
+  attribute \src "simple/issuer.py:160"
   wire width 2 \fsm_state
-  attribute \src "simple/issuer.py:157"
+  attribute \src "simple/issuer.py:160"
   wire width 2 \fsm_state$next
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $13
+  attribute \src "simple/issuer.py:165"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbg_core_stop_o
+    connect \Y $13
+  end
+  process $group_18
+    assign \core_msr__ren$next \core_msr__ren
+    assign \core_msr__ren$next 2'00
+    attribute \src "simple/issuer.py:160"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:163"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:165"
+        switch { $13 }
+          attribute \src "simple/issuer.py:165"
+          case 1'1
+            assign \core_msr__ren$next 2'10
+        end
+      attribute \src "simple/issuer.py:182"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:206"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \core_msr__ren$next 2'00
+    end
+    sync init
+      update \core_msr__ren 2'00
+    sync posedge \clk
+      update \core_msr__ren \core_msr__ren$next
+  end
+  attribute \src "simple/issuer.py:116"
+  wire width 1 \pc_changed
+  attribute \src "simple/issuer.py:116"
+  wire width 1 \pc_changed$next
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $9
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $10
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \core_fast_nia_wen
-    connect \Y $9
+    connect \A \core_state_nia_wen
+    connect \Y $15
   end
-  process $group_16
+  process $group_19
     assign \pc_changed$next \pc_changed
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
         assign \pc_changed$next 1'0
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
-        attribute \src "simple/issuer.py:209"
-        switch { $9 }
-          attribute \src "simple/issuer.py:209"
+        attribute \src "simple/issuer.py:211"
+        switch { $15 }
+          attribute \src "simple/issuer.py:211"
           case 1'1
             assign \pc_changed$next 1'1
         end
@@ -176523,145 +170443,145 @@ module \test_issuer
     sync posedge \clk
       update \pc_changed \pc_changed$next
   end
-  attribute \src "simple/issuer.py:162"
-  wire width 1 $11
-  attribute \src "simple/issuer.py:162"
-  cell $not $12
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $17
+  attribute \src "simple/issuer.py:165"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $11
+    connect \Y $17
   end
-  process $group_17
+  process $group_20
     assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-        attribute \src "simple/issuer.py:162"
-        switch { $11 }
-          attribute \src "simple/issuer.py:162"
+        attribute \src "simple/issuer.py:165"
+        switch { $17 }
+          attribute \src "simple/issuer.py:165"
           case 1'1
             assign \imem_a_pc_i \pc [47:0]
         end
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:162"
-  wire width 1 $13
-  attribute \src "simple/issuer.py:162"
-  cell $not $14
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $19
+  attribute \src "simple/issuer.py:165"
+  cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $13
+    connect \Y $19
   end
-  process $group_18
+  process $group_21
     assign \imem_a_valid_i 1'0
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-        attribute \src "simple/issuer.py:162"
-        switch { $13 }
-          attribute \src "simple/issuer.py:162"
+        attribute \src "simple/issuer.py:165"
+        switch { $19 }
+          attribute \src "simple/issuer.py:165"
           case 1'1
             assign \imem_a_valid_i 1'1
         end
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
             assign \imem_a_valid_i 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:162"
-  wire width 1 $15
-  attribute \src "simple/issuer.py:162"
-  cell $not $16
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $21
+  attribute \src "simple/issuer.py:165"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $15
+    connect \Y $21
   end
-  process $group_19
+  process $group_22
     assign \imem_f_valid_i 1'0
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-        attribute \src "simple/issuer.py:162"
-        switch { $15 }
-          attribute \src "simple/issuer.py:162"
+        attribute \src "simple/issuer.py:165"
+        switch { $21 }
+          attribute \src "simple/issuer.py:165"
           case 1'1
             assign \imem_f_valid_i 1'1
         end
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
             assign \imem_f_valid_i 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:162"
-  wire width 1 $17
-  attribute \src "simple/issuer.py:162"
-  cell $not $18
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $23
+  attribute \src "simple/issuer.py:165"
+  cell $not $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $17
+    connect \Y $23
   end
-  process $group_20
+  process $group_23
     assign \cur_pc$next \cur_pc
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-        attribute \src "simple/issuer.py:162"
-        switch { $17 }
-          attribute \src "simple/issuer.py:162"
+        attribute \src "simple/issuer.py:165"
+        switch { $23 }
+          attribute \src "simple/issuer.py:165"
           case 1'1
             assign \cur_pc$next \pc
         end
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
@@ -176675,56 +170595,96 @@ module \test_issuer
     sync posedge \clk
       update \cur_pc \cur_pc$next
   end
-  attribute \src "simple/issuer.py:162"
-  wire width 1 $19
-  attribute \src "simple/issuer.py:162"
-  cell $not $20
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $25
+  attribute \src "simple/issuer.py:165"
+  cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \dbg_core_stop_o
-    connect \Y $19
+    connect \Y $25
   end
-  attribute \src "simple/issuer.py:211"
-  wire width 1 $21
-  attribute \src "simple/issuer.py:211"
-  cell $not $22
+  process $group_24
+    assign \cur_msr$next \cur_msr
+    attribute \src "simple/issuer.py:160"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:163"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:165"
+        switch { $25 }
+          attribute \src "simple/issuer.py:165"
+          case 1'1
+            assign \cur_msr$next \core_msr__data_o
+        end
+      attribute \src "simple/issuer.py:182"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:206"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \clk
+      update \cur_msr \cur_msr$next
+  end
+  attribute \src "simple/issuer.py:165"
+  wire width 1 $27
+  attribute \src "simple/issuer.py:165"
+  cell $not $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbg_core_stop_o
+    connect \Y $27
+  end
+  attribute \src "simple/issuer.py:213"
+  wire width 1 $29
+  attribute \src "simple/issuer.py:213"
+  cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $21
+    connect \Y $29
   end
-  process $group_21
+  process $group_25
     assign \fsm_state$next \fsm_state
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-        attribute \src "simple/issuer.py:162"
-        switch { $19 }
-          attribute \src "simple/issuer.py:162"
+        attribute \src "simple/issuer.py:165"
+        switch { $27 }
+          attribute \src "simple/issuer.py:165"
           case 1'1
             assign \fsm_state$next 2'01
         end
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
             assign \fsm_state$next 2'10
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
-        attribute \src "simple/issuer.py:211"
-        switch { $21 }
-          attribute \src "simple/issuer.py:211"
+        attribute \src "simple/issuer.py:213"
+        switch { $29 }
+          attribute \src "simple/issuer.py:213"
           case 1'1
             assign \fsm_state$next 2'00
         end
@@ -176739,14 +170699,14 @@ module \test_issuer
     sync posedge \clk
       update \fsm_state \fsm_state$next
   end
-  attribute \src "simple/issuer.py:112"
+  attribute \src "simple/issuer.py:115"
   wire width 32 \current_insn
-  attribute \src "simple/issuer.py:185"
-  wire width 32 $23
+  attribute \src "simple/issuer.py:193"
+  wire width 32 $31
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  wire width 7 $24
+  wire width 7 $32
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $25
+  cell $mul $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -176754,47 +170714,47 @@ module \test_issuer
     parameter \Y_WIDTH 7
     connect \A \cur_pc [2]
     connect \B 6'100000
-    connect \Y $24
+    connect \Y $32
   end
-  attribute \src "simple/issuer.py:185"
-  cell $shift $26
+  attribute \src "simple/issuer.py:193"
+  cell $shift $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 32
     connect \A \imem_f_instr_o
-    connect \B $24
-    connect \Y $23
+    connect \B $32
+    connect \Y $31
   end
-  process $group_22
+  process $group_26
     assign \current_insn 32'00000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
-            assign \current_insn $23
+            assign \current_insn $31
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:205"
-  wire width 1 $27
-  attribute \src "simple/issuer.py:205"
-  cell $ne $28
+  attribute \src "simple/issuer.py:207"
+  wire width 1 $35
+  attribute \src "simple/issuer.py:207"
+  cell $ne $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -176802,110 +170762,110 @@ module \test_issuer
     parameter \Y_WIDTH 1
     connect \A \core_insn_type
     connect \B 7'0000001
-    connect \Y $27
+    connect \Y $35
   end
-  process $group_23
+  process $group_27
     assign \core_valid 1'0
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
             assign \core_valid 1'1
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
-        attribute \src "simple/issuer.py:205"
-        switch { $27 }
-          attribute \src "simple/issuer.py:205"
+        attribute \src "simple/issuer.py:207"
+        switch { $35 }
+          attribute \src "simple/issuer.py:207"
           case 1'1
             assign \core_valid 1'1
         end
     end
     sync init
   end
-  process $group_24
+  process $group_28
     assign \core_issue_i 1'0
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
             assign \core_issue_i 1'1
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:115"
+  attribute \src "simple/issuer.py:118"
   wire width 32 \ilatch
-  attribute \src "simple/issuer.py:115"
+  attribute \src "simple/issuer.py:118"
   wire width 32 \ilatch$next
-  process $group_25
+  process $group_29
     assign \core_raw_opcode_in 32'00000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
             assign \core_raw_opcode_in \current_insn
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
         assign \core_raw_opcode_in \ilatch
     end
     sync init
   end
-  process $group_26
+  process $group_30
     assign \ilatch$next \ilatch
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
             assign \ilatch$next \current_insn
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
     end
@@ -176919,202 +170879,119 @@ module \test_issuer
     sync posedge \clk
       update \ilatch \ilatch$next
   end
-  process $group_27
-    assign \core_msr__ren 8'00000000
-    attribute \src "simple/issuer.py:157"
-    switch \fsm_state
-      attribute \src "simple/issuer.py:160"
-      attribute \nmigen.decoding "IDLE/0"
-      case 2'00
-      attribute \src "simple/issuer.py:174"
-      attribute \nmigen.decoding "INSN_READ/1"
-      case 2'01
-        attribute \src "simple/issuer.py:175"
-        switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
-          case 1'1
-          attribute \src "simple/issuer.py:179"
-          case
-            assign \core_msr__ren 8'00000010
-        end
-      attribute \src "simple/issuer.py:204"
-      attribute \nmigen.decoding "INSN_ACTIVE/2"
-      case 2'10
-    end
-    sync init
-  end
-  attribute \src "simple/issuer.py:118"
-  wire width 64 \msr
-  process $group_28
-    assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
-    switch \fsm_state
-      attribute \src "simple/issuer.py:160"
-      attribute \nmigen.decoding "IDLE/0"
-      case 2'00
-      attribute \src "simple/issuer.py:174"
-      attribute \nmigen.decoding "INSN_READ/1"
-      case 2'01
-        attribute \src "simple/issuer.py:175"
-        switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
-          case 1'1
-          attribute \src "simple/issuer.py:179"
-          case
-            assign \msr \core_msr__data_o
-        end
-      attribute \src "simple/issuer.py:204"
-      attribute \nmigen.decoding "INSN_ACTIVE/2"
-      case 2'10
-    end
-    sync init
-  end
   process $group_31
-    assign \core_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \core_dec2_pc 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
+    assign \core_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-        attribute \src "simple/issuer.py:175"
+        attribute \src "simple/issuer.py:183"
         switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
+          attribute \src "simple/issuer.py:183"
           case 1'1
-          attribute \src "simple/issuer.py:179"
+          attribute \src "simple/issuer.py:187"
           case
-            assign \core_dec2_msr \msr
-            assign \core_dec2_pc \cur_pc
+            assign { \core_dec2_msr \core_dec2_pc } { \cur_msr \cur_pc }
         end
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
         assign { \core_dec2_msr \core_dec2_pc } { \cur_msr \cur_pc }
     end
     sync init
   end
-  process $group_30
-    assign \cur_msr$next \cur_msr
-    attribute \src "simple/issuer.py:157"
-    switch \fsm_state
-      attribute \src "simple/issuer.py:160"
-      attribute \nmigen.decoding "IDLE/0"
-      case 2'00
-      attribute \src "simple/issuer.py:174"
-      attribute \nmigen.decoding "INSN_READ/1"
-      case 2'01
-        attribute \src "simple/issuer.py:175"
-        switch { \imem_f_busy_o }
-          attribute \src "simple/issuer.py:175"
-          case 1'1
-          attribute \src "simple/issuer.py:179"
-          case
-            assign \cur_msr$next \msr
-        end
-      attribute \src "simple/issuer.py:204"
-      attribute \nmigen.decoding "INSN_ACTIVE/2"
-      case 2'10
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \cur_msr \cur_msr$next
-  end
-  attribute \src "simple/issuer.py:211"
-  wire width 1 $29
-  attribute \src "simple/issuer.py:211"
-  cell $not $30
+  attribute \src "simple/issuer.py:213"
+  wire width 1 $37
+  attribute \src "simple/issuer.py:213"
+  cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $29
+    connect \Y $37
   end
-  attribute \src "simple/issuer.py:215"
-  wire width 1 $31
-  attribute \src "simple/issuer.py:215"
-  cell $not $32
+  attribute \src "simple/issuer.py:217"
+  wire width 1 $39
+  attribute \src "simple/issuer.py:217"
+  cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $31
+    connect \Y $39
   end
-  process $group_32
-    assign \core_wen 8'00000000
-    attribute \src "simple/issuer.py:157"
+  process $group_33
+    assign \core_wen 2'00
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
-        attribute \src "simple/issuer.py:211"
-        switch { $29 }
-          attribute \src "simple/issuer.py:211"
+        attribute \src "simple/issuer.py:213"
+        switch { $37 }
+          attribute \src "simple/issuer.py:213"
           case 1'1
-            attribute \src "simple/issuer.py:215"
-            switch { $31 }
-              attribute \src "simple/issuer.py:215"
+            attribute \src "simple/issuer.py:217"
+            switch { $39 }
+              attribute \src "simple/issuer.py:217"
               case 1'1
-                assign \core_wen 8'00000001
+                assign \core_wen 2'01
             end
         end
     end
     sync init
   end
-  attribute \src "simple/issuer.py:211"
-  wire width 1 $33
-  attribute \src "simple/issuer.py:211"
-  cell $not $34
+  attribute \src "simple/issuer.py:213"
+  wire width 1 $41
+  attribute \src "simple/issuer.py:213"
+  cell $not $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $33
+    connect \Y $41
   end
-  attribute \src "simple/issuer.py:215"
-  wire width 1 $35
-  attribute \src "simple/issuer.py:215"
-  cell $not $36
+  attribute \src "simple/issuer.py:217"
+  wire width 1 $43
+  attribute \src "simple/issuer.py:217"
+  cell $not $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $35
+    connect \Y $43
   end
-  process $group_33
+  process $group_34
     assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:157"
+    attribute \src "simple/issuer.py:160"
     switch \fsm_state
-      attribute \src "simple/issuer.py:160"
+      attribute \src "simple/issuer.py:163"
       attribute \nmigen.decoding "IDLE/0"
       case 2'00
-      attribute \src "simple/issuer.py:174"
+      attribute \src "simple/issuer.py:182"
       attribute \nmigen.decoding "INSN_READ/1"
       case 2'01
-      attribute \src "simple/issuer.py:204"
+      attribute \src "simple/issuer.py:206"
       attribute \nmigen.decoding "INSN_ACTIVE/2"
       case 2'10
-        attribute \src "simple/issuer.py:211"
-        switch { $33 }
-          attribute \src "simple/issuer.py:211"
+        attribute \src "simple/issuer.py:213"
+        switch { $41 }
+          attribute \src "simple/issuer.py:213"
           case 1'1
-            attribute \src "simple/issuer.py:215"
-            switch { $35 }
-              attribute \src "simple/issuer.py:215"
+            attribute \src "simple/issuer.py:217"
+            switch { $43 }
+              attribute \src "simple/issuer.py:217"
               case 1'1
                 assign \core_data_i \nia
             end
@@ -177122,12 +170999,12 @@ module \test_issuer
     end
     sync init
   end
-  attribute \src "simple/issuer.py:226"
-  wire width 128 $37
-  attribute \src "simple/issuer.py:226"
-  wire width 128 $38
-  attribute \src "simple/issuer.py:226"
-  cell $sshl $39
+  attribute \src "simple/issuer.py:228"
+  wire width 128 $45
+  attribute \src "simple/issuer.py:228"
+  wire width 128 $46
+  attribute \src "simple/issuer.py:228"
+  cell $sshl $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -177135,34 +171012,34 @@ module \test_issuer
     parameter \Y_WIDTH 128
     connect \A 1'1
     connect \B \dbg_dbg_gpr_addr
-    connect \Y $38
+    connect \Y $46
   end
-  connect $37 $38
-  process $group_34
+  connect $45 $46
+  process $group_35
     assign \core_dmi__ren 32'00000000000000000000000000000000
-    attribute \src "simple/issuer.py:223"
+    attribute \src "simple/issuer.py:225"
     switch { \dbg_dbg_gpr_req }
-      attribute \src "simple/issuer.py:223"
+      attribute \src "simple/issuer.py:225"
       case 1'1
-        assign \core_dmi__ren $37 [31:0]
+        assign \core_dmi__ren $45 [31:0]
     end
     sync init
   end
-  process $group_35
+  process $group_36
     assign \dbg_dbg_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:223"
+    attribute \src "simple/issuer.py:225"
     switch { \dbg_dbg_gpr_req }
-      attribute \src "simple/issuer.py:223"
+      attribute \src "simple/issuer.py:225"
       case 1'1
         assign \dbg_dbg_gpr_data \core_dmi__data_o
     end
     sync init
   end
-  process $group_36
+  process $group_37
     assign \dbg_dbg_gpr_ack 1'0
-    attribute \src "simple/issuer.py:223"
+    attribute \src "simple/issuer.py:225"
     switch { \dbg_dbg_gpr_req }
-      attribute \src "simple/issuer.py:223"
+      attribute \src "simple/issuer.py:225"
       case 1'1
         assign \dbg_dbg_gpr_ack 1'1
     end
-- 
2.30.2