From 3bcfea378d522ca9bf687ef5013e57901a5c2f3d Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Thu, 28 Jan 2021 15:02:22 +0100 Subject: [PATCH] Working bench design with SRAM in top block. --- experiments12/Makefile | 3 +- experiments12/SPBlock_512W64B8W.v | 3 + experiments12/coriolis2/katana.py | 8 --- experiments12/coriolis2/settings.py | 97 +++++++++++++---------------- experiments12/memory.py | 10 +-- 5 files changed, 53 insertions(+), 68 deletions(-) create mode 100644 experiments12/SPBlock_512W64B8W.v diff --git a/experiments12/Makefile b/experiments12/Makefile index acd76db..5be0fc9 100755 --- a/experiments12/Makefile +++ b/experiments12/Makefile @@ -2,7 +2,7 @@ LOGICAL_SYNTHESIS = Yosys PHYSICAL_SYNTHESIS = Coriolis - DESIGN_KIT = sxlib + DESIGN_KIT = FlexLib018 # YOSYS_FLATTEN = Yes CHIP = chip @@ -17,6 +17,7 @@ USE_KITE = No # RM_CHIP = Yes + YOSYS_BLACKBOXES = SPBlock_512W64B8W NETLISTS = $(shell cat nets.txt) # PATTERNS = memory_r diff --git a/experiments12/SPBlock_512W64B8W.v b/experiments12/SPBlock_512W64B8W.v new file mode 100644 index 0000000..008d877 --- /dev/null +++ b/experiments12/SPBlock_512W64B8W.v @@ -0,0 +1,3 @@ +(* blackbox = 1 *) +module SPBlock_512W64B8W(input [8:0] a, input [63:0] d, output [63:0] q, input [7:0] we, input clk); +endmodule // SPBlock_512W64B8W diff --git a/experiments12/coriolis2/katana.py b/experiments12/coriolis2/katana.py index 442b2fc..80b8383 100644 --- a/experiments12/coriolis2/katana.py +++ b/experiments12/coriolis2/katana.py @@ -2,11 +2,3 @@ from Hurricane import DebugSession #DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) ) -#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) ) diff --git a/experiments12/coriolis2/settings.py b/experiments12/coriolis2/settings.py index 85b6b47..6b73bee 100644 --- a/experiments12/coriolis2/settings.py +++ b/experiments12/coriolis2/settings.py @@ -1,58 +1,47 @@ # -*- Mode:Python -*- import os -import Cfg -import CRL -import Viewer -#import node180.scn6m_deep_09 -import symbolic.cmos -from helpers import l, u, n - - -Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile ) - - -Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) - -Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False ) -Cfg.getParamBool ( 'misc.info' ).setBool ( False ) -Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False ) -Cfg.getParamBool ( 'misc.bug' ).setBool ( False ) -Cfg.getParamBool ( 'misc.logMode' ).setBool ( True ) -Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True ) -Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True ) -#Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 ) -#Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 ) -Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 ) -Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 ) -Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 ) -Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True ) -Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 ) -Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 ) -Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL4') -Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 ) -Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 ) -Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 ) -#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) ) - -Cfg.Configuration.popDefaultPriority() - -#cellsTop = os.path.abspath( os.getcwd()+'/../cells' ) -if os.environ.has_key('CELLS_TOP'): - cellsTop = os.environ['CELLS_TOP'] -else: - cellsTop = '../../../cells' - -af = CRL.AllianceFramework.get() -env = af.getEnvironment() -env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend ) -env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend ) -#env.setCLOCK( '^clk$|m_clock' ) -env.setCLOCK( 'clk|ck|cki' ) -env.setPOWER( 'vdd' ) -env.setGROUND( 'vss' ) - -Cfg.Configuration.popDefaultPriority() - -print 'Successfully read user configuration' +import socket +import helpers + +NdaDirectory = None +if os.environ.has_key('NDA_TOP'): + NdaDirectory = os.environ['NDA_TOP'] +if not NdaDirectory: + hostname = socket.gethostname() + if hostname.startswith('lepka'): + NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno' + if not os.path.isdir(NdaDirectory): + print '[ERROR] You forgot to mount the NDA encrypted directory, stupid!' + else: + NdaDirectory = '/users/soft/techno/techno' +helpers.setNdaTopDir( NdaDirectory ) +import Cfg +from CRL import AllianceFramework +from helpers import overlay, l, u, n +from NDA.node180.tsmc_c018 import techno, FlexLib, LibreSOCIO, LibreSOCMem + +techno.setup() +FlexLib.setup() +LibreSOCIO.setup() +LibreSOCMem.setup() + +with overlay.CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.etesian.graphics = 3 + cfg.conductor.stopLevel = 0 + cfg.conductor.maxPlaceIterations = 2 + cfg.conductor.useFixedAbHeight = False + env = AllianceFramework.get().getEnvironment() + env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) + env.setPOWER ('vdd') + env.setGROUND('vss') + +print( ' o Successfully run "<>/coriolis2/settings.py".' ) diff --git a/experiments12/memory.py b/experiments12/memory.py index 81782dd..b540359 100644 --- a/experiments12/memory.py +++ b/experiments12/memory.py @@ -1,9 +1,10 @@ -from nmigen import Elaboratable, Cat, Module, Signal, Instance +from nmigen import Elaboratable, Cat, Module, Signal, ClockSignal, Instance from nmigen.cli import rtlil class ADD(Elaboratable): def __init__(self, width): + self.we = Signal(8) self.a = Signal(width) self.b = Signal(width) self.f = Signal(width) @@ -17,8 +18,7 @@ class ADD(Elaboratable): a = Signal(9) q = Signal(64) # output d = Signal(64) # input - we = Signal(8) - sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we) + sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=self.we, i_clk=ClockSignal()) m.submodules += sram # connect up some arbitrary signals @@ -35,5 +35,5 @@ def create_ilang(dut, ports, test_name): f.write(vl) if __name__ == "__main__": - alu = ADD(width=4) - create_ilang(alu, [alu.a, alu.b, alu.f], "memory") + alu = ADD(width=64) + create_ilang(alu, [alu.a, alu.b, alu.f, alu.we], "memory") -- 2.30.2