From 3bd2acbd6ad7a2cae991ac9726d665e03dd84e05 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Nov 2018 00:08:15 +0000 Subject: [PATCH] corrections, clash fetch_action and self.fetch_action --- cpu_fetch_stage.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py index 469b21e..1fa8942 100644 --- a/cpu_fetch_stage.py +++ b/cpu_fetch_stage.py @@ -55,10 +55,10 @@ class CPUFetchStage(Module): fetch_pc = Signal(32, reset=reset_vector) - self.sync += If(fetch_action != fetch_action_wait, + self.sync += If(self.fetch_action != fetch_action_wait, self.output_pc.eq(fetch_pc)) - memory_interface_fetch_address = fetch_pc[2:] + self.memory_interface_fetch_address = fetch_pc[2:] #initial output_pc <= reset_vector; #initial output_state <= `fetch_output_state_empty; @@ -75,7 +75,7 @@ class CPUFetchStage(Module): self.output_instruction.eq(self.memory_interface_fetch_data) ) - self.sync += delayed_instruction_valid.eq(fetch_action == + self.sync += delayed_instruction_valid.eq(self.fetch_action == fetch_action_wait) fc = { @@ -106,7 +106,8 @@ class CPUFetchStage(Module): } fc[fetch_action_default] = fc[fetch_action_ack_trap] fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap] - self.sync += Case(fetch_action, fc).makedefault(fetch_action_default) + self.sync += Case(self.fetch_action, + fc).makedefault(fetch_action_default) if __name__ == "__main__": example = CPUFetchStage() -- 2.30.2