From 3c17238bc9fe8a078a6199470291f07bab9c64c8 Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Thu, 9 May 2019 10:29:22 +0100 Subject: [PATCH] [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand. --- gas/ChangeLog | 5 +++++ gas/config/tc-aarch64.c | 1 + include/ChangeLog | 6 ++++++ include/opcode/aarch64.h | 2 ++ opcodes/ChangeLog | 16 ++++++++++++++++ opcodes/aarch64-asm-2.c | 21 +++++++++++---------- opcodes/aarch64-asm.c | 6 ++++-- opcodes/aarch64-dis-2.c | 21 +++++++++++---------- opcodes/aarch64-dis.c | 11 +++++++++++ opcodes/aarch64-opc-2.c | 5 +++-- opcodes/aarch64-opc.c | 18 ++++++++++++------ opcodes/aarch64-tbl.h | 7 +++++-- 12 files changed, 87 insertions(+), 32 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 65cc8d1d9b3..4e968452e93 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2019-05-09 Matthew Malcomson + + * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 + operand. + 2019-05-09 Matthew Malcomson * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 054935ef6cf..7bf73fd9c3c 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5787,6 +5787,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_SHLIMM_UNPRED: case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: + case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: case AARCH64_OPND_SVE_SIMM5: case AARCH64_OPND_SVE_SIMM5B: case AARCH64_OPND_SVE_SIMM6: diff --git a/include/ChangeLog b/include/ChangeLog index 600e753f060..3b389d54485 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2019-05-09 Matthew Malcomson + + * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 + operand. + (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. + 2019-05-09 Matthew Malcomson * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9cc73cad223..bd6b845a134 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -394,6 +394,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ + AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ @@ -597,6 +598,7 @@ enum aarch64_insn_class sve_size_bh, sve_size_sd2, sve_size_013, + sve_shift_tsz_hsd, testbranch, cryptosm3, cryptosm4, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a8051cd5002..2ab1845dc55 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,19 @@ +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-asm.c (aarch64_ins_sve_shrimm): + (aarch64_encode_variant_using_iclass): Handle + sve_shift_tsz_hsd iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_shift_tsz_hsd iclass decode. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_SHRIMM_UNPRED_22. + (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 + operand. + 2019-05-09 Matthew Malcomson * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index ac5bda40f32..00ab9b370ed 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -638,7 +638,6 @@ aarch64_insert_operand (const aarch64_operand *self, case 169: case 170: case 171: - case 184: case 185: case 186: case 187: @@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 190: case 191: case 192: - case 197: - case 200: + case 193: + case 198: + case 201: return aarch64_ins_regno (self, info, code, inst, errors); case 14: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 203: + case 204: return aarch64_ins_reglane (self, info, code, inst, errors); case 35: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -696,7 +696,6 @@ aarch64_insert_operand (const aarch64_operand *self, case 82: case 159: case 161: - case 176: case 177: case 178: case 179: @@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 181: case 182: case 183: - case 202: + case 184: + case 203: return aarch64_ins_imm (self, info, code, inst, errors); case 43: case 44: @@ -845,16 +845,17 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 174: case 175: + case 176: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 193: case 194: case 195: case 196: + case 197: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 198: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 199: - case 201: + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 200: + case 202: return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 0ec27b24928..6be17f9246e 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1241,8 +1241,9 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self, const aarch64_opnd_info *prev_operand; unsigned int esize; - assert (info->idx > 0); - prev_operand = &inst->operands[info->idx - 1]; + unsigned int opnd_backshift = get_operand_specific_data (self); + assert (info->idx >= (int)opnd_backshift); + prev_operand = &inst->operands[info->idx - opnd_backshift]; esize = aarch64_get_qualifier_esize (prev_operand->qualifier); insert_all_fields (self, code, 16 * esize - info->imm.value); return TRUE; @@ -1624,6 +1625,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) case sve_index: case sve_shift_pred: case sve_shift_unpred: + case sve_shift_tsz_hsd: /* For indices and shift amounts, the variant is encoded as part of the immediate. */ break; diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index e6952bd7a29..d70a29095bf 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -20069,7 +20069,6 @@ aarch64_extract_operand (const aarch64_operand *self, case 169: case 170: case 171: - case 184: case 185: case 186: case 187: @@ -20078,8 +20077,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 190: case 191: case 192: - case 197: - case 200: + case 193: + case 198: + case 201: return aarch64_ext_regno (self, info, code, inst, errors); case 9: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 203: + case 204: return aarch64_ext_reglane (self, info, code, inst, errors); case 35: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -20132,7 +20132,6 @@ aarch64_extract_operand (const aarch64_operand *self, case 82: case 159: case 161: - case 176: case 177: case 178: case 179: @@ -20140,7 +20139,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 181: case 182: case 183: - case 202: + case 184: + case 203: return aarch64_ext_imm (self, info, code, inst, errors); case 43: case 44: @@ -20283,16 +20283,17 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 174: case 175: + case 176: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 193: case 194: case 195: case 196: + case 197: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 198: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 199: - case 201: + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 200: + case 202: return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 1a727a4ba84..5571ab6c98f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2832,6 +2832,17 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = i; break; + case sve_shift_tsz_hsd: + i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); + if (i == 0) + return FALSE; + while (i != 1) + { + i >>= 1; + variant += 1; + } + break; + default: /* No mapping between instruction class and qualifiers. */ return TRUE; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index eef857eff1e..3c0e13a0fb9 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -198,8 +198,9 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1f85294e3bf..84e30f5f345 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2540,13 +2540,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: - size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier); - if (!value_in_range_p (opnd->imm.value, 1, 8 * size)) + case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: { - set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size); - return 0; - } - break; + unsigned int index = + (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1; + size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier); + if (!value_in_range_p (opnd->imm.value, 1, 8 * size)) + { + set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size); + return 0; + } + break; + } default: break; @@ -3352,6 +3357,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_SHLIMM_UNPRED: case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: + case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: case AARCH64_OPND_SVE_SIMM5: case AARCH64_OPND_SVE_SIMM5B: case AARCH64_OPND_SVE_SIMM6: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ba5d6b579fc..6f8f47a664d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4923,10 +4923,13 @@ struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ - Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ - Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \ F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ + Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB, \ + F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ + "a shift-right immediate operand") \ Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ "a 5-bit signed immediate") \ Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ -- 2.30.2