From 3c1ea6e65122197b9ef67e16ca8f5758ac9d6800 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 17 May 2016 13:46:51 -0700 Subject: [PATCH] vc4: Fix vc4_nir_lower_io for non-vec4 I/O. To support GLSL-to-NIR, we need to be able to support actual float/vec2/vec3 varyings. --- src/gallium/drivers/vc4/vc4_nir_lower_io.c | 34 ++++++++-------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c b/src/gallium/drivers/vc4/vc4_nir_lower_io.c index d61c95a6b5d..4a795f8da0f 100644 --- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c +++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c @@ -26,8 +26,8 @@ #include "util/u_format.h" /** - * Walks the NIR generated by TGSI-to-NIR to lower its io intrinsics into - * something amenable to the VC4 architecture. + * Walks the NIR generated by TGSI-to-NIR or GLSL-to-NIR to lower its io + * intrinsics into something amenable to the VC4 architecture. * * Currently, it splits VS inputs and uniforms into scalars, drops any * non-position outputs in coordinate shaders, and fixes up the addressing on @@ -36,17 +36,17 @@ */ static void -replace_intrinsic_with_vec4(nir_builder *b, nir_intrinsic_instr *intr, - nir_ssa_def **comps) +replace_intrinsic_with_vec(nir_builder *b, nir_intrinsic_instr *intr, + nir_ssa_def **comps) { - /* Batch things back together into a vec4. This will get split by the - * later ALU scalarization pass. + /* Batch things back together into a vector. This will get split by + * the later ALU scalarization pass. */ - nir_ssa_def *vec = nir_vec4(b, comps[0], comps[1], comps[2], comps[3]); + nir_ssa_def *vec = nir_vec(b, comps, intr->num_components); /* Replace the old intrinsic with a reference to our reconstructed - * vec4. + * vector. */ nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_src_for_ssa(vec)); nir_instr_remove(&intr->instr); @@ -177,9 +177,6 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b, enum pipe_format format = c->vs_key->attr_formats[attr]; uint32_t attr_size = util_format_get_blocksize(format); - /* All TGSI-to-NIR inputs are vec4. */ - assert(intr->num_components == 4); - /* We only accept direct outputs and TGSI only ever gives them to us * with an offset value of 0. */ @@ -210,7 +207,7 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b, util_format_description(format); nir_ssa_def *dests[4]; - for (int i = 0; i < 4; i++) { + for (int i = 0; i < intr->num_components; i++) { uint8_t swiz = desc->swizzle[i]; dests[i] = vc4_nir_get_vattr_channel_vpm(c, b, vpm_reads, swiz, desc); @@ -226,7 +223,7 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b, } } - replace_intrinsic_with_vec4(b, intr, dests); + replace_intrinsic_with_vec(b, intr, dests); } static bool @@ -325,16 +322,9 @@ static void vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b, nir_intrinsic_instr *intr) { - /* All TGSI-to-NIR uniform loads are vec4, but we need byte offsets - * in the backend. - */ - if (intr->num_components == 1) - return; - assert(intr->num_components == 4); - b->cursor = nir_before_instr(&intr->instr); - /* Generate scalar loads equivalent to the original VEC4. */ + /* Generate scalar loads equivalent to the original vector. */ nir_ssa_def *dests[4]; for (unsigned i = 0; i < intr->num_components; i++) { nir_intrinsic_instr *intr_comp = @@ -359,7 +349,7 @@ vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b, nir_builder_instr_insert(b, &intr_comp->instr); } - replace_intrinsic_with_vec4(b, intr, dests); + replace_intrinsic_with_vec(b, intr, dests); } static void -- 2.30.2