From 3c1f1a6605a4463117ba358fc9528c4999628b81 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 16:25:59 -0700 Subject: [PATCH] Fix ordering of when to insert zero index --- passes/techmap/pmux2shiftx.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index f8cdf5783..6ffc27a4c 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -65,8 +65,7 @@ struct Pmux2ShiftxPass : public Pass { const int clog2width = ceil(log2(s_width)); RTLIL::SigSpec pmux_b; - pmux_b.append(RTLIL::Const(0, clog2width)); - for (int i = s_width-1; i > 0; i--) + for (int i = s_width-1; i >= 0; i--) pmux_b.append(RTLIL::Const(i, clog2width)); shiftx_a.append(cell->getPort("\\B")); pmux_s.append(cell->getPort("\\S")); -- 2.30.2