From 3c20bead498f5deaafa031dffde34ecf387f30da Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Oct 2018 13:10:39 +0100 Subject: [PATCH] clarify bitwidth --- simple_v_extension/specification.mdwn | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index ec17b082a..fa8eb6b85 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1243,9 +1243,19 @@ rd bitwidths). The pseudo-code is therefore as follows: uint64_t l; } el_reg_t; + bw(elwidth): + if elwidth == 0: + return xlen + if elwidth == 1: + return xlen / 2 + if elwidth == 2: + return xlen * 2 + // elwidth == 3: + return 8 + get_max_elwidth(rs1, rs2): - return max(int_csr[rs1].elwidth, # default (XLEN) if not set - int_csr[rs2].elwidth) # again XLEN if no entry + return max(bw(int_csr[rs1].elwidth), # default (XLEN) if not set + bw(int_csr[rs2].elwidth)) # again XLEN if no entry get_polymorphed_reg(reg, bitwidth, offset): el_reg_t res; -- 2.30.2