From 3c2f1be9d2112df031ad6e73740b1fe985cb29ee Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 7 Jul 2020 16:17:20 +0200 Subject: [PATCH] Update cke => clk_en in test --- gram/test/test_dfii.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index 475e980..6bb238e 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -128,17 +128,17 @@ class DFIInjectorTestCase(FHDLTestCase): return (m, dut, csrhost) - def test_cke(self): + def test_clk_en(self): m, dut, csrhost = self.generate_dfiinjector() def process(): yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 1), sel=0xF) yield - self.assertTrue((yield dut.master.phases[0].cke[0])) + self.assertTrue((yield dut.master.phases[0].clk_en[0])) yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) yield - self.assertFalse((yield dut.master.phases[0].cke[0])) + self.assertFalse((yield dut.master.phases[0].clk_en[0])) runSimulation(m, process, "test_dfiinjector.vcd") -- 2.30.2