From 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 May 2020 13:13:01 +0200 Subject: [PATCH] build/xilinx/vivado: ensure Vivado process our .xdc early. When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the PCIe lanes to default locations that do not necessarily match the ones used in the design. Processing our constraints earlier makes Vivado use our constraints and not the ones from the generated wrapper. --- litex/build/xilinx/vivado.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 2a8b91d2..70cf5c80 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -167,6 +167,7 @@ class XilinxVivadoToolchain: # Add constraints tcl.append("\n# Add constraints\n") tcl.append("read_xdc {}.xdc".format(build_name)) + tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(build_name)) # Add pre-synthesis commands tcl.append("\n# Add pre-synthesis commands\n") @@ -276,7 +277,7 @@ class XilinxVivadoToolchain: "-to [get_pins -filter {{REF_PIN_NAME == PRE}} " "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" ) - # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs + # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs platform.add_platform_command( "set_max_delay 2 -quiet " "-from [get_pins -filter {{REF_PIN_NAME == C}} " -- 2.30.2