From 3c3532bfe8139ae2f935bf42b89e5935bfbe5b00 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Jun 2022 19:34:13 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 63fb9d500..fbc3f1e83 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -374,8 +374,9 @@ Register Hazards at the element level. This goes back to the fundamental principle that SV is nothing more than a Sub-Program-Counter sitting between Decode and Issue phases. +For Scalar Reduction, Microarchitectures *may* take opportunities to parallelise the reduction -but only if in doing so they preserve Program Order at the Element Level. +but only if in doing so they preserve strict Program Order at the Element Level. Opportunities where this is possible include an `OR` operation or a MIN/MAX operation: it may be possible to parallelise the reduction, but for Floating Point it is not permitted due to different results -- 2.30.2