From 3c3e8a88d5db2871af9af4b43ec001245f615f39 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Feb 2021 16:36:39 +0000 Subject: [PATCH] ordering wrong on svstate in ISACaller --- src/soc/decoder/isa/caller.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 03bf16d2..59b665e2 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -686,6 +686,8 @@ class ISACaller: yield self.dec2.dec.bigendian.eq(self.bigendian) yield self.dec2.state.msr.eq(self.msr.value) yield self.dec2.state.pc.eq(pc) + # sigh TODO + #yield self.dec2.state.svstate.eq(self.svstate.spr.value) # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set yield Settle() -- 2.30.2