From 3c425869fd36a73a040e07b58050069c6022b0de Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Jul 2020 13:53:28 +0100 Subject: [PATCH] make cxxsim optional and print warning --- src/soc/fu/alu/test/test_pipe_caller.py | 11 +++++++++-- src/soc/fu/shift_rot/test/test_pipe_caller.py | 10 +++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index a8a62f1c..d905f68c 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -1,8 +1,15 @@ from nmigen import Module, Signal from nmigen.back.pysim import Delay, Settle -cxxsim = True +# NOTE: to use this (set to True), at present it is necessary to check +# out the cxxsim nmigen branch +cxxsim = False if cxxsim: - from nmigen.sim.cxxsim import Simulator + try: + from nmigen.sim.cxxsim import Simulator + except ImportError: + print("nope, sorry, have to use nmigen cxxsim branch for now") + cxxsim = False + from nmigen.back.pysim import Simulator else: from nmigen.back.pysim import Simulator diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index fdb2089a..4abdfd12 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,10 +1,18 @@ from nmigen import Module, Signal from nmigen.back.pysim import Delay, Settle +# NOTE: to use this (set to True), at present it is necessary to check +# out the cxxsim nmigen branch cxxsim = False if cxxsim: - from nmigen.sim.cxxsim import Simulator + try: + from nmigen.sim.cxxsim import Simulator + except ImportError: + print("nope, sorry, have to use nmigen cxxsim branch for now") + cxxsim = False + from nmigen.back.pysim import Simulator else: from nmigen.back.pysim import Simulator + from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -- 2.30.2