From 3c4ff655917c05c66995e472fde799919ee4dbfd Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 29 Mar 2022 01:06:51 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 7ba682add..92c335cd9 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -163,6 +163,13 @@ The name "weird" refers to a minor violation of SV rules when it comes to derivi Normally the progression of the SV for-loop would move on to the next register. Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination. +Further useful violation of the normal SV Elwidth override rules allows +for packing of multiple CR test results into an Integer Element. Note +that the CR (source operand) elwidth field is utilised to determine the bit- +packing size (1/2/4/8 with remaining bits within the Integer element +set to zero) whilst the INT (dest operand) elwidth field still sets +the Integer element size as usual (8/16/32/default) + crrweird: RT, BB, mask.mode for i in range(VL): -- 2.30.2