From 3c5605957ced2d0c745413b8da1bb1d864600690 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Wed, 25 Mar 2020 16:21:08 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA
 and RISC-V

---
 25/977be26323c3b11e78631fb8a0e3357b2a8ed5 | 83 +++++++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 25/977be26323c3b11e78631fb8a0e3357b2a8ed5

diff --git a/25/977be26323c3b11e78631fb8a0e3357b2a8ed5 b/25/977be26323c3b11e78631fb8a0e3357b2a8ed5
new file mode 100644
index 0000000..e68cd60
--- /dev/null
+++ b/25/977be26323c3b11e78631fb8a0e3357b2a8ed5
@@ -0,0 +1,83 @@
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+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Wed, 25 Mar 2020 16:21:08 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: mtnolan2640@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-186-13-XFc87XHKjY@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
+References: <bug-186-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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-- 
2.30.2