From 3c65f5ff7893bb34696c476abacfe34ad739bf18 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 16 May 2020 17:50:46 -0400 Subject: [PATCH] Add ilang output to test_maskgen.py --- src/soc/shift_rot/test/test_maskgen.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/shift_rot/test/test_maskgen.py b/src/soc/shift_rot/test/test_maskgen.py index f9d28d70..1a4d34e6 100644 --- a/src/soc/shift_rot/test/test_maskgen.py +++ b/src/soc/shift_rot/test/test_maskgen.py @@ -1,6 +1,7 @@ from nmigen import Signal, Module from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.test.utils import FHDLTestCase +from nmigen.cli import rtlil from soc.alu.maskgen import MaskGen from soc.decoder.helpers import MASK import random @@ -37,5 +38,11 @@ class MaskGenTestCase(FHDLTestCase): with sim.write_vcd("maskgen.vcd", "maskgen.gtkw", traces=dut.ports()): sim.run() + def test_ilang(self): + dut = MaskGen(64) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("maskgen.il", "w") as f: + f.write(vl) + if __name__ == '__main__': unittest.main() -- 2.30.2