From 3c70c2cfa94bf75fdaf81d653f3b47f0def99b93 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 Jun 2020 21:56:24 +0100 Subject: [PATCH] whitespace cleanup --- src/soc/minerva/test/test_cache.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/minerva/test/test_cache.py b/src/soc/minerva/test/test_cache.py index 02e16e55..4c273b6b 100644 --- a/src/soc/minerva/test/test_cache.py +++ b/src/soc/minerva/test/test_cache.py @@ -1,5 +1,4 @@ from nmigen import Elaboratable, Module, Signal, Record -from nmigen.utils import log2_int from nmutil.formaltest import FHDLTestCase from nmigen.asserts import AnyConst, AnySeq, Assert, Assume, Past, Initial @@ -49,12 +48,14 @@ class L1CacheSpec(Elaboratable): with m.If(cache.bus_re): with m.If(cache.bus_valid): - # Lines are refilled with an incremental burst that starts at the missed address + # Lines are refilled with an incremental burst that + # starts at the missed address # and wraps around the offset bits. m.d.sync += spec_bus_addr.offset.eq(spec_bus_addr.offset + 1) with m.If((cache.bus_addr == cache.s2_addr) & ~cache.bus_error): m.d.sync += spec_s2_rdata.eq(cache.bus_rdata) - # A burst ends when all words in the line have been refilled, or an error occured. + # A burst ends when all words in the line have + # been refilled, or an error occured. m.d.comb += spec_bus_last.eq(cache.bus_addr.offset == last_offset) with m.If(cache.bus_valid & cache.bus_last | cache.bus_error): m.d.sync += spec_bus_re.eq(0) -- 2.30.2