From 3c70c83f9b31549a1fb48091dcaef5fb0993b6bc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 May 2020 12:35:12 +0200 Subject: [PATCH] cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. --- litex/soc/cores/cpu/blackparrot/system.h | 5 +- litex/soc/cores/cpu/lm32/system.h | 21 +++- litex/soc/cores/cpu/microwatt/system.h | 4 +- litex/soc/cores/cpu/minerva/system.h | 5 +- .../base => cores/cpu/mor1kx}/spr-defs.h | 10 +- litex/soc/cores/cpu/mor1kx/system.h | 51 ++++++-- litex/soc/cores/cpu/picorv32/system.h | 4 +- litex/soc/cores/cpu/rocket/system.h | 4 +- litex/soc/cores/cpu/serv/system.h | 4 +- litex/soc/cores/cpu/vexriscv/system.h | 27 ++++- litex/soc/software/libbase/system.c | 111 ------------------ 11 files changed, 105 insertions(+), 141 deletions(-) rename litex/soc/{software/include/base => cores/cpu/mor1kx}/spr-defs.h (99%) diff --git a/litex/soc/cores/cpu/blackparrot/system.h b/litex/soc/cores/cpu/blackparrot/system.h index cccdb54d..079c7cfd 100644 --- a/litex/soc/cores/cpu/blackparrot/system.h +++ b/litex/soc/cores/cpu/blackparrot/system.h @@ -5,10 +5,9 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ void flush_l2_cache(void); - void busy_wait(unsigned int ms); #include diff --git a/litex/soc/cores/cpu/lm32/system.h b/litex/soc/cores/cpu/lm32/system.h index 989c9c62..1272cf1a 100644 --- a/litex/soc/cores/cpu/lm32/system.h +++ b/litex/soc/cores/cpu/lm32/system.h @@ -5,8 +5,25 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void) +{ + asm volatile( + "wcsr ICC, r0\n" + "nop\n" + "nop\n" + "nop\n" + "nop\n" + ); +} + +__attribute__((unused)) static void flush_cpu_dcache(void) +{ + asm volatile( + "wcsr DCC, r0\n" + "nop\n" + ); +} + void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/cores/cpu/microwatt/system.h b/litex/soc/cores/cpu/microwatt/system.h index 989c9c62..941dc564 100644 --- a/litex/soc/cores/cpu/microwatt/system.h +++ b/litex/soc/cores/cpu/microwatt/system.h @@ -5,8 +5,8 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/cores/cpu/minerva/system.h b/litex/soc/cores/cpu/minerva/system.h index cccdb54d..408ab365 100644 --- a/litex/soc/cores/cpu/minerva/system.h +++ b/litex/soc/cores/cpu/minerva/system.h @@ -5,10 +5,9 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ void flush_l2_cache(void); - void busy_wait(unsigned int ms); #include diff --git a/litex/soc/software/include/base/spr-defs.h b/litex/soc/cores/cpu/mor1kx/spr-defs.h similarity index 99% rename from litex/soc/software/include/base/spr-defs.h rename to litex/soc/cores/cpu/mor1kx/spr-defs.h index e073a506..4dbc3b1c 100644 --- a/litex/soc/software/include/base/spr-defs.h +++ b/litex/soc/cores/cpu/mor1kx/spr-defs.h @@ -1,8 +1,8 @@ /* spr-defs.h - Special purpose registers definitions file - + Copyright (C) 2000 Damjan Lampret Copyright (C) 2008, 2010 Embecosm Limited - + Contributor Damjan Lampret Contributor Jeremy Bennett @@ -184,10 +184,10 @@ #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ #define SPR_CPUCFGR_ND 0x00000400 /* No delay-slot */ #define SPR_CPUCFGR_AVRP 0x00000800 /* Architecture version register present */ -#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception vector base address register +#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception vector base address register present */ #define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-specific registers present */ -#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic exception control/status +#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic exception control/status registers present */ #define SPR_CPUCFGR_RES 0xffff8000 /* Reserved */ @@ -628,7 +628,7 @@ #define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ #define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ -/* +/* * Bit definitions for the Power management register * */ diff --git a/litex/soc/cores/cpu/mor1kx/system.h b/litex/soc/cores/cpu/mor1kx/system.h index 004a00e3..77366810 100644 --- a/litex/soc/cores/cpu/mor1kx/system.h +++ b/litex/soc/cores/cpu/mor1kx/system.h @@ -1,17 +1,12 @@ #ifndef __SYSTEM_H #define __SYSTEM_H +#include + #ifdef __cplusplus extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); -void flush_l2_cache(void); - -void busy_wait(unsigned int ms); - -#include static inline unsigned long mfspr(unsigned long add) { unsigned long ret; @@ -26,6 +21,48 @@ static inline void mtspr(unsigned long add, unsigned long val) __asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val)); } +__attribute__((unused)) static void flush_cpu_icache(void) +{ + unsigned long iccfgr; + unsigned long cache_set_size; + unsigned long cache_ways; + unsigned long cache_block_size; + unsigned long cache_size; + int i; + + iccfgr = mfspr(SPR_ICCFGR); + cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); + cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; + cache_size = cache_set_size * cache_ways * cache_block_size; + + for (i = 0; i < cache_size; i += cache_block_size) + mtspr(SPR_ICBIR, i); +} + +__attribute__((unused)) static void flush_cpu_dcache(void) +{ + unsigned long dccfgr; + unsigned long cache_set_size; + unsigned long cache_ways; + unsigned long cache_block_size; + unsigned long cache_size; + int i; + + dccfgr = mfspr(SPR_DCCFGR); + cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW); + cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); + cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; + cache_size = cache_set_size * cache_ways * cache_block_size; + + for (i = 0; i < cache_size; i += cache_block_size) + mtspr(SPR_DCBIR, i); +} + +void flush_l2_cache(void); + +void busy_wait(unsigned int ms); + #ifdef __cplusplus } #endif diff --git a/litex/soc/cores/cpu/picorv32/system.h b/litex/soc/cores/cpu/picorv32/system.h index 989c9c62..afa56d67 100644 --- a/litex/soc/cores/cpu/picorv32/system.h +++ b/litex/soc/cores/cpu/picorv32/system.h @@ -5,8 +5,8 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/cores/cpu/rocket/system.h b/litex/soc/cores/cpu/rocket/system.h index cccdb54d..d3e98e1d 100644 --- a/litex/soc/cores/cpu/rocket/system.h +++ b/litex/soc/cores/cpu/rocket/system.h @@ -5,8 +5,8 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){} /* FIXME: do something useful here! */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/cores/cpu/serv/system.h b/litex/soc/cores/cpu/serv/system.h index 989c9c62..afa56d67 100644 --- a/litex/soc/cores/cpu/serv/system.h +++ b/litex/soc/cores/cpu/serv/system.h @@ -5,8 +5,8 @@ extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */ +__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */ void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h index cccdb54d..952b5b32 100644 --- a/litex/soc/cores/cpu/vexriscv/system.h +++ b/litex/soc/cores/cpu/vexriscv/system.h @@ -1,12 +1,35 @@ #ifndef __SYSTEM_H #define __SYSTEM_H +#include + #ifdef __cplusplus extern "C" { #endif -void flush_cpu_icache(void); -void flush_cpu_dcache(void); +__attribute__((unused)) static void flush_cpu_icache(void) +{ + asm volatile( + ".word(0x400F)\n" + "nop\n" + "nop\n" + "nop\n" + "nop\n" + "nop\n" + ); +} + +__attribute__((unused)) static void flush_cpu_dcache(void) +{ + unsigned long cache_info; + asm volatile ("csrr %0, %1" : "=r"(cache_info) : "i"(CSR_DCACHE_INFO)); + unsigned long cache_way_size = cache_info & 0xFFFFF; + unsigned long cache_line_size = (cache_info >> 20) & 0xFFF; + for(register unsigned long idx = 0;idx < cache_way_size;idx += cache_line_size){ + asm volatile("mv x10, %0 \n .word(0b01110000000001010101000000001111)"::"r"(idx)); + } +} + void flush_l2_cache(void); void busy_wait(unsigned int ms); diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c index 49d23ac6..f9e37eb2 100644 --- a/litex/soc/software/libbase/system.c +++ b/litex/soc/software/libbase/system.c @@ -12,117 +12,6 @@ #include #include -void flush_cpu_icache(void) -{ -#if defined (__lm32__) - asm volatile( - "wcsr ICC, r0\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - ); -#elif defined (__or1k__) - unsigned long iccfgr; - unsigned long cache_set_size; - unsigned long cache_ways; - unsigned long cache_block_size; - unsigned long cache_size; - int i; - - iccfgr = mfspr(SPR_ICCFGR); - cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); - cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); - cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; - cache_size = cache_set_size * cache_ways * cache_block_size; - - for (i = 0; i < cache_size; i += cache_block_size) - mtspr(SPR_ICBIR, i); -#elif defined (__picorv32__) - /* no instruction cache */ - asm volatile("nop"); -#elif defined (__vexriscv__) - asm volatile( - ".word(0x400F)\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - "nop\n" - ); -#elif defined (__minerva__) - /* no instruction cache */ - asm volatile("nop"); -#elif defined (__rocket__) - /* FIXME: do something useful here! */ - asm volatile("nop"); -#elif defined (__microwatt__) - /* FIXME: do something useful here! */ - asm volatile("nop"); -#elif defined (__blackparrot__) - /* TODO: BP do something useful here! */ - asm volatile("nop"); -#elif defined (__serv__) - /* no instruction cache */ -#else -#error Unsupported architecture -#endif -} - -void flush_cpu_dcache(void) -{ -#if defined (__lm32__) - asm volatile( - "wcsr DCC, r0\n" - "nop\n" - ); -#elif defined (__or1k__) - unsigned long dccfgr; - unsigned long cache_set_size; - unsigned long cache_ways; - unsigned long cache_block_size; - unsigned long cache_size; - int i; - - dccfgr = mfspr(SPR_DCCFGR); - cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW); - cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); - cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; - cache_size = cache_set_size * cache_ways * cache_block_size; - - for (i = 0; i < cache_size; i += cache_block_size) - mtspr(SPR_DCBIR, i); -#elif defined (__picorv32__) - /* no data cache */ - asm volatile("nop"); -#elif defined (__vexriscv__) - unsigned long cache_info; - asm volatile ("csrr %0, %1" : "=r"(cache_info) : "i"(CSR_DCACHE_INFO)); - unsigned long cache_way_size = cache_info & 0xFFFFF; - unsigned long cache_line_size = (cache_info >> 20) & 0xFFF; - for(register unsigned long idx = 0;idx < cache_way_size;idx += cache_line_size){ - asm volatile("mv x10, %0 \n .word(0b01110000000001010101000000001111)"::"r"(idx)); - } -#elif defined (__minerva__) - /* no data cache */ - asm volatile("nop"); -#elif defined (__rocket__) - /* FIXME: do something useful here! */ - asm volatile("nop"); -#elif defined (__microwatt__) - /* FIXME: do something useful here! */ - asm volatile("nop"); -/*SC_add: What BB does here?*/ -#elif defined (__blackparrot__) - /* FIXME: do something useful here! */ - asm volatile("nop"); -#elif defined (__serv__) - /* no data cache */ -#else -#error Unsupported architecture -#endif -} - #ifdef CONFIG_L2_SIZE void flush_l2_cache(void) { -- 2.30.2