From 3c9acf89fda9dbce3e2b49318c35c87f860af5b0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Aug 2022 15:17:26 +0100 Subject: [PATCH] okaaaay, long story. using GPR(_RT) <- something will *not* get detected by parser.py as an output register. therefore, the modified registers were (SVSTATE, CTR) *not* (RT, SVSTATE, CTR). this resulted in *SVSTATE* being tested for Rc=1, not RT. added unit tests to catch "setvl." --- openpower/isa/simplev.mdwn | 4 +- .../decoder/isa/test_caller_setvl.py | 74 +++++++++++++++++++ 2 files changed, 76 insertions(+), 2 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 648f43d8..b78063dd 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -29,7 +29,7 @@ Pseudo-code: if (vf & (¬vs) & ¬(ms)) = 1 then step <- SVSTATE_NEXT(SVi, 0b0) if _RT != 0 then - GPR(_RT) <- [0]*57 || step + RT <- [0]*57 || step else VLimm <- SVi + 1 # set or get MVL @@ -47,7 +47,7 @@ Pseudo-code: SVSTATE[0:6] <- MVL SVSTATE[7:13] <- VL if _RT != 0 then - GPR(_RT) <- [0]*57 || VL + RT <- [0]*57 || VL if ((¬vs) & ¬(ms)) = 0 then # set requested Vertical-First mode, clear persist SVSTATE[63] <- vf diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index be118bd8..45ff3578 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -23,6 +23,80 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + def test_1_setvl_zero_rc1(self): + lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl + # but, ha! r4 (RA) is zero. and Rc=1. therefore, CR0 should be set EQ + svstate = SVP64State() + svstate.maxvl = 5 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + print (" vfirst", bin(sim.svstate.vfirst)) + self.assertEqual(sim.svstate.vl, 0) + self.assertEqual(sim.svstate.maxvl, 5) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) + self.assertEqual(sim.svstate.vfirst, 0) + print(" gpr4", sim.gpr(4)) + self.assertEqual(sim.gpr(4), SelectableInt(0, 64)) + print(" gpr5", sim.gpr(5)) + self.assertEqual(sim.gpr(5), SelectableInt(0, 64)) + CR0 = sim.crl[0] + print(" CR0", bin(CR0.get_range().value)) + self.assertEqual(CR0[CRFields.EQ], 1) + self.assertEqual(CR0[CRFields.LT], 0) + self.assertEqual(CR0[CRFields.GT], 0) + self.assertEqual(CR0[CRFields.SO], 0) + + def test_2_setvl_nonzero_rc1(self): + lst = SVP64Asm(["setvl. 5, 4, 5, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl + # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT + svstate = SVP64State() + svstate.maxvl = 5 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + initial_regs = [0] * 32 + initial_regs[4] = 4 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_regs=initial_regs) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + print (" vfirst", bin(sim.svstate.vfirst)) + self.assertEqual(sim.svstate.vl, 4) + self.assertEqual(sim.svstate.maxvl, 5) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) + self.assertEqual(sim.svstate.vfirst, 0) + print(" gpr4", sim.gpr(4)) + self.assertEqual(sim.gpr(4), SelectableInt(4, 64)) + print(" gpr5", sim.gpr(5)) + self.assertEqual(sim.gpr(5), SelectableInt(4, 64)) + CR0 = sim.crl[0] + print(" CR0", bin(CR0.get_range().value)) + self.assertEqual(CR0[CRFields.EQ], 0) + self.assertEqual(CR0[CRFields.LT], 0) + self.assertEqual(CR0[CRFields.GT], 1) + self.assertEqual(CR0[CRFields.SO], 0) + def test_svstep_1(self): lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode) "setvl 0, 0, 1, 1, 0, 0", # svstep -- 2.30.2