From 3c9f496337f754f7c22afb46b017871db5844a97 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 14 Aug 2019 10:48:50 +0000 Subject: [PATCH] [AArch64] Add SVE conditional integer unary patterns This patch adds patterns to match conditional unary operations on integers. At the moment we rely on combine to merge separate arithmetic and vcond_mask operations, and since the latter doesn't accept zero operands, we miss out on the opportunity to use the movprfx /z alternative. (This alternative is tested by the ACLE patches though.) 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*cond__2): New pattern. (*cond__any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/cond_unary_1.c: New test. * gcc.target/aarch64/sve/cond_unary_1_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4_run.c: Likewise. Co-Authored-By: Kugan Vivekanandarajah From-SVN: r274476 --- gcc/ChangeLog | 7 +++ gcc/config/aarch64/aarch64-sve.md | 39 +++++++++++++++ gcc/testsuite/ChangeLog | 12 +++++ .../gcc.target/aarch64/sve/cond_unary_1.c | 44 +++++++++++++++++ .../gcc.target/aarch64/sve/cond_unary_1_run.c | 27 +++++++++++ .../gcc.target/aarch64/sve/cond_unary_2.c | 43 +++++++++++++++++ .../gcc.target/aarch64/sve/cond_unary_2_run.c | 28 +++++++++++ .../gcc.target/aarch64/sve/cond_unary_3.c | 43 +++++++++++++++++ .../gcc.target/aarch64/sve/cond_unary_3_run.c | 27 +++++++++++ .../gcc.target/aarch64/sve/cond_unary_4.c | 47 +++++++++++++++++++ .../gcc.target/aarch64/sve/cond_unary_4_run.c | 27 +++++++++++ 11 files changed, 344 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 401b2bcb6fc..4184b0f0ed2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-08-14 Richard Sandiford + Kugan Vivekanandarajah + + * config/aarch64/aarch64-sve.md + (*cond__2): New pattern. + (*cond__any): Likewise. + 2019-08-14 Richard Sandiford * config/aarch64/iterators.md (SVE_COND_FP_ABS_CMP): New iterator. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index b9ef8dd2a3a..bed8da9f8ba 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1454,6 +1454,45 @@ "\t%0., %1/m, %2." ) +;; Predicated integer unary arithmetic, merging with the first input. +(define_insn "*cond__2" + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") + (unspec:SVE_I + [(match_operand: 1 "register_operand" "Upl, Upl") + (SVE_INT_UNARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "0, w")) + (match_dup 2)] + UNSPEC_SEL))] + "TARGET_SVE" + "@ + \t%0., %1/m, %0. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] +) + +;; Predicated integer unary arithmetic, merging with an independent value. +;; +;; The earlyclobber isn't needed for the first alternative, but omitting +;; it would only help the case in which operands 2 and 3 are the same, +;; which is handled above rather than here. Marking all the alternatives +;; as earlyclobber helps to make the instruction more regular to the +;; register allocator. +(define_insn "*cond__any" + [(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_I + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (SVE_INT_UNARY:SVE_I + (match_operand:SVE_I 2 "register_operand" "w, w, w")) + (match_operand:SVE_I 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] + UNSPEC_SEL))] + "TARGET_SVE && !rtx_equal_p (operands[2], operands[3])" + "@ + \t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. + movprfx\t%0, %3\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Logical inverse ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a9c98219a35..cf0f7a0be09 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2019-08-14 Richard Sandiford + Kugan Vivekanandarajah + + * gcc.target/aarch64/sve/cond_unary_1.c: New test. + * gcc.target/aarch64/sve/cond_unary_1_run.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_2_run.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_3.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_3_run.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_4.c: Likewise. + * gcc.target/aarch64/sve/cond_unary_4_run.c: Likewise. + 2019-08-14 Bob Duff * gnat.dg/alignment15.adb: New testcase. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c new file mode 100644 index 00000000000..2705a76530c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include + +#define abs(A) ((A) < 0 ? -(A) : (A)) +#define neg(A) (-(A)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : a[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, abs) \ + T (TYPE, neg) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* XFAILed because the ?: gets canonicalized so that the operation is in + the false arm. */ +/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c new file mode 100644 index 00000000000..a6c1a49dd1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_unary_1.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : a[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c new file mode 100644 index 00000000000..3d346fb23ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include + +#define abs(A) ((A) < 0 ? -(A) : (A)) +#define neg(A) (-(A)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict b, \ + TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : b[i]; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, abs) \ + T (TYPE, neg) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c new file mode 100644 index 00000000000..1a385c323bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_unary_2.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], b[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c new file mode 100644 index 00000000000..ab2e99a0341 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include + +#define abs(A) ((A) < 0 ? -(A) : (A)) +#define neg(A) (-(A)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : 5; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, abs) \ + T (TYPE, neg) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c new file mode 100644 index 00000000000..3c72b239acf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_unary_3.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : 5)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c new file mode 100644 index 00000000000..5ad0d809aea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include + +#define abs(A) ((A) < 0 ? -(A) : (A)) +#define neg(A) (-(A)) + +#define DEF_LOOP(TYPE, OP) \ + void __attribute__ ((noipa)) \ + test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \ + TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? OP (a[i]) : 0; \ + } + +#define TEST_TYPE(T, TYPE) \ + T (TYPE, abs) \ + T (TYPE, neg) + +#define TEST_ALL(T) \ + TEST_TYPE (T, int8_t) \ + TEST_TYPE (T, int16_t) \ + TEST_TYPE (T, int32_t) \ + TEST_TYPE (T, int64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* Really we should be able to use MOVPRFX /z here, but at the moment + we're relying on combine to merge a SEL and an arithmetic operation, + and the SEL doesn't allow the "false" value to be zero when the "true" + value is a register. */ +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c new file mode 100644 index 00000000000..48d2541508a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize" } */ + +#include "cond_unary_4.c" + +#define N 99 + +#define TEST_LOOP(TYPE, OP) \ + { \ + TYPE r[N], a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##TYPE##_##OP (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? OP (a[i]) : 0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} -- 2.30.2