From 3cba7139dca6ad8105751338c7693e6f1c6d3e5e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 06:31:27 +0100 Subject: [PATCH] rv_add in lh/sh --- riscv/insns/lh.h | 2 +- riscv/insns/lhu.h | 2 +- riscv/insns/lwu.h | 2 +- riscv/insns/sh.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h index 0d458e0..0ac4b9a 100644 --- a/riscv/insns/lh.h +++ b/riscv/insns/lh.h @@ -1 +1 @@ -WRITE_RD(MMU.load_int16(RS1 + insn.i_imm())); +WRITE_RD(MMU.load_int16(rv_add(RS1, insn.i_imm()))); diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h index 9d24070..b428ffa 100644 --- a/riscv/insns/lhu.h +++ b/riscv/insns/lhu.h @@ -1 +1 @@ -WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm())); +WRITE_RD(MMU.load_uint16(rv_add(RS1, insn.i_imm()))); diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index dcc4d75..f0e46a2 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1,2 +1,2 @@ require_rv64; -WRITE_RD(MMU.load_uint32(RS1 + insn.i_imm())); +WRITE_RD(MMU.load_uint32(rv_add(RS1, insn.i_imm()))); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h index 22aa3a8..e216392 100644 --- a/riscv/insns/sh.h +++ b/riscv/insns/sh.h @@ -1 +1 @@ -MMU.store_uint16(RS1 + insn.s_imm(), RS2); +MMU.store_uint16(rv_add(RS1, insn.s_imm()), RS2); -- 2.30.2