From 3cc1c209a2079c052be7c64c5b22598ec2393c45 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Dec 2021 00:03:33 +0000 Subject: [PATCH] bug in mmu setting radix tree size with one extra bit rts does not include bit 63 (MSB0 bit 0) --- src/soc/experiment/mmu.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index d9136b48..8eeb361f 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -190,8 +190,8 @@ class MMU(Elaboratable): comb += pt_valid.eq(r.pt0_valid) # rts == radix tree size, number of address bits - # being translated. takes bits 5:7 and 61:63 - comb += rts.eq(Cat(pgtbl.rts2, pgtbl.rts1, pgtbl.hr)) + # being translated. takes bits 5:7 and 61:62 + comb += rts.eq(Cat(pgtbl.rts2, pgtbl.rts1, Const(0))) # mbits == number of address bits to index top # level of tree. takes bits 0:4 @@ -293,7 +293,7 @@ class MMU(Elaboratable): comb += v.pt0_valid.eq(1) # rts == radix tree size, # address bits being translated - comb += rts.eq(Cat(prtbl.rts2, prtbl.rts1, prtbl.rsv1)) + comb += rts.eq(Cat(prtbl.rts2, prtbl.rts1, Const(0))) # mbits == # address bits to index top level of tree comb += mbits.eq(prtbl.rpds) -- 2.30.2