From 3cd49ba3ba82391f6586495fc0e429828bb7c149 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 21:27:42 +0100 Subject: [PATCH] missing ports from issuer, when doing verilog --- src/soc/simple/issuer.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 38f94077..1b8d82eb 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -198,6 +198,11 @@ class TestIssuer(Elaboratable): yield self.memerr_o yield from self.core.ports() yield from self.imem.ports() + yield self.core_start_i + yield self.core_stop_i + yield self.core_bigendian_i + yield self.busy_o + yield self.halted_o def ports(self): return list(self) -- 2.30.2