From 3cf46671e9322f6e19e9c288038985c7747aa63a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 5 Aug 2015 10:33:08 +0200 Subject: [PATCH] liteeth/phy: rename rgmii to s6rgmii since specific to Spartan6 Also remove autodetection support for RGMII. For it to work we would need to pass the device we are building for. --- misoclib/com/liteeth/phy/__init__.py | 5 ++--- misoclib/com/liteeth/phy/{rgmii.py => s6rgmii.py} | 2 ++ 2 files changed, 4 insertions(+), 3 deletions(-) rename misoclib/com/liteeth/phy/{rgmii.py => s6rgmii.py} (99%) diff --git a/misoclib/com/liteeth/phy/__init__.py b/misoclib/com/liteeth/phy/__init__.py index 8974ddbd..05414a13 100644 --- a/misoclib/com/liteeth/phy/__init__.py +++ b/misoclib/com/liteeth/phy/__init__.py @@ -17,9 +17,8 @@ def LiteEthPHY(clock_pads, pads, **kwargs): from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII return LiteEthPHYGMII(clock_pads, pads, **kwargs) elif hasattr(pads, "rx_ctl"): - # This is a 10/100/1G RGMII PHY - from misoclib.com.liteeth.phy.rgmii import LiteEthPHYRGMII - return LiteEthPHYRGMII(clock_pads, pads, **kwargs) + # This is a 10/100/1G RGMII PHY + raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation") elif flen(pads.tx_data) == 4: # This is a MII PHY from misoclib.com.liteeth.phy.mii import LiteEthPHYMII diff --git a/misoclib/com/liteeth/phy/rgmii.py b/misoclib/com/liteeth/phy/s6rgmii.py similarity index 99% rename from misoclib/com/liteeth/phy/rgmii.py rename to misoclib/com/liteeth/phy/s6rgmii.py index 2fd015e5..dc25ea78 100644 --- a/misoclib/com/liteeth/phy/rgmii.py +++ b/misoclib/com/liteeth/phy/s6rgmii.py @@ -1,3 +1,5 @@ +# RGMII PHY for Spartan-6 + from migen.genlib.io import DDROutput from migen.genlib.misc import WaitTimer from migen.genlib.fsm import FSM, NextState -- 2.30.2