From 3d02baf2f4497d85556ecab7dfdd1fb2b7aeae04 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Jun 2020 12:59:14 +0100
Subject: [PATCH] add cesar nice finds to resources

---
 resources.mdwn | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/resources.mdwn b/resources.mdwn
index 5cb632503..bb143ddac 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -290,6 +290,19 @@ Some learning resources I found in the community:
 * <https://wiki.f-si.org/index.php/FSiC2019>
 * <https://fusesoc.net>
 * <https://www.lowrisc.org/open-silicon/>
+* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
+* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
+  Synchronous Resets? Asynchronous Resets? I am so confused! How will I
+  ever know which to use? by Clifford E. Cummings
+* <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
+  Clock Domain Crossing (CDC) Design & Verification Techniques Using
+  SystemVerilog, by Clifford E. Cummings
+  In particular, see section 5.8.2: Multi-bit CDC signal passing using
+  1-deep / 2-register FIFO synchronizer.
+* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
+  Understanding Latency Hiding on GPUs, by Vasily Volkov
+
 
 # Real/Physical Projects
 
-- 
2.30.2