From 3d07a60c0254889bef8cd6fa774c1dc8c3aaf47c Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Thu, 7 Jun 2018 03:05:44 +0530
Subject: [PATCH] arch-power: Add fixed-point doubleword load and store
 instructions

This adds the following load and store instructions:
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I57a95003b6c6cfc09cc40f9ac03b32a8dfd7b26d
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
 src/arch/power/isa/decoder.isa     | 19 ++++++++++++++
 src/arch/power/isa/formats/mem.isa | 40 ++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 85b554172..0615b93e9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -150,6 +150,21 @@ decode PO default Unknown::unknown() {
     58: decode DS_XO {
         format LoadDispShiftOp {
             2: lwa({{ Rt = Mem_sw; }});
+            0: ld({{ Rt = Mem; }});
+        }
+
+        format LoadDispShiftUpdateOp {
+            1: ldu({{ Rt = Mem; }});
+        }
+    }
+
+    62: decode DS_XO {
+        format StoreDispShiftOp {
+            0: std({{ Mem = Rs; }});
+        }
+
+        format StoreDispShiftUpdateOp {
+            1: stdu({{ Mem = Rs; }});
         }
     }
 
@@ -252,6 +267,7 @@ decode PO default Unknown::unknown() {
             23: lwzx({{ Rt = Mem_uw; }});
             341: lwax({{ Rt = Mem_sw; }});
             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
+            21: ldx({{ Rt = Mem; }});
             535: lfsx({{ Ft_sf = Mem_sf; }});
             599: lfdx({{ Ft = Mem_df; }});
             855: lfiwax({{ Ft_uw = Mem; }});
@@ -263,6 +279,7 @@ decode PO default Unknown::unknown() {
             375: lhaux({{ Rt = Mem_sh; }});
             55: lwzux({{ Rt = Mem_uw; }});
             373: lwaux({{ Rt = Mem_sw; }});
+            53: ldux({{ Rt = Mem; }});
             567: lfsux({{ Ft_sf = Mem_sf; }});
             631: lfdux({{ Ft = Mem_df; }});
         }
@@ -287,12 +304,14 @@ decode PO default Unknown::unknown() {
                 CR = cr;
                 Rsv = 0;
             }});
+            149: stdx({{ Mem = Rs }});
         }
 
         format StoreIndexUpdateOp {
             247: stbux({{ Mem_ub = Rs_ub; }});
             439: sthux({{ Mem_uh = Rs_uh; }});
             183: stwux({{ Mem_uw = Rs_uw; }});
+            181: stdux({{ Mem = Rs; }});
         }
 
         format IntOp {
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index bd99a683c..201417746 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -306,6 +306,16 @@ def format LoadDispShiftOp(memacc_code,
 }};
 
 
+def format StoreDispShiftOp(memacc_code,
+                            ea_code = {{ EA = Ra + (disp << 2); }},
+                            ea_code_ra0 = {{ EA = (disp << 2); }},
+                            mem_flags = [], inst_flags = []) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+                 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
 def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                             mem_flags = [], inst_flags = []) {{
 
@@ -332,3 +342,33 @@ def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                       base_class = 'MemDispOp',
                       exec_template_base = 'Store')
 }};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+                                 ea_code = {{ EA = Ra + (disp << 2); }},
+                                 mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+                                  ea_code = {{ EA = Ra + (disp << 2); }},
+                                  mem_flags = [], inst_flags = []) {{
+
+    # Add in the update code
+    memacc_code += 'Ra = EA;'
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+                      base_class = 'MemDispShiftOp',
+                      exec_template_base = 'Store')
+}};
-- 
2.30.2