From 3d14be23fa58008aa8ed012295cd4d6fe3b45eb2 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 30 Nov 2023 23:27:48 -0800 Subject: [PATCH] caller.py: implement exit_group syscall --- src/openpower/decoder/isa/caller.py | 8 ++++++++ src/openpower/test/runner.py | 11 +++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 409fedfb..53412e99 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1141,6 +1141,10 @@ class StepLoop: log(" new dststep", dststep) +class ExitSyscallCalled(Exception): + pass + + class SyscallEmulator(openpower.syscalls.Dispatcher): def __init__(self, isacaller): self.__isacaller = isacaller @@ -1155,6 +1159,10 @@ class SyscallEmulator(openpower.syscalls.Dispatcher): (identifier, *arguments) = map(int, (identifier, *arguments)) return super().__call__(identifier, *arguments) + def sys_exit_group(self, status, *rest): + self.__isacaller.halted = True + raise ExitSyscallCalled(status) + class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): # decoder2 - an instance of power_decoder2 diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index 6c6163b0..a2aac7f0 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -27,6 +27,7 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmutil.gtkw import write_gtkw from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ExitSyscallCalled from openpower.endian import bigendian from openpower.decoder.power_decoder2 import PowerDecode2 @@ -106,7 +107,10 @@ class SimRunner(StateRunner): # call simulated operation log("sim", code) - yield from sim.execute_one() + try: + yield from sim.execute_one() + except ExitSyscallCalled: + break yield Settle() index = sim.pc.CIA.value//4 @@ -273,7 +277,10 @@ class TestRunnerBase(FHDLTestCase): log("sprs", test.sprs, kind=LogType.InstrInOuts) log("cr", test.cr, kind=LogType.InstrInOuts) log("mem", test.mem) - log("msr", test.msr, kind=LogType.InstrInOuts) + if test.msr is None: + log("msr", "None", kind=LogType.InstrInOuts) + else: + log("msr", hex(test.msr), kind=LogType.InstrInOuts) def format_assembly(assembly): # type: (str) -> str -- 2.30.2