From 3d43e6d6215e04ebc5b4a51a579284c9c2fdc659 Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 20 Aug 2019 12:27:19 +0000 Subject: [PATCH] vendor.lattice_ecp5: add Diamond support. --- nmigen/vendor/lattice_ecp5.py | 148 +++++++++++++++++++++++++++++++--- 1 file changed, 138 insertions(+), 10 deletions(-) diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index 833cd7b..1d2d9b0 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -9,6 +9,9 @@ __all__ = ["LatticeECP5Platform"] class LatticeECP5Platform(TemplatedPlatform): """ + Trellis toolchain + ----------------- + Required tools: * ``yosys`` * ``nextpnr-ecp5`` @@ -34,13 +37,37 @@ class LatticeECP5Platform(TemplatedPlatform): * ``{{name}}.config``: ASCII bitstream. * ``{{name}}.bit``: binary bitstream. * ``{{name}}.svf``: JTAG programming vector. + + Diamond toolchain + ----------------- + + Required tools: + * ``pnmainc`` + * ``ddtcmd`` + + The environment is populated by running the script specified in the environment variable + ``NMIGEN_Diamond_env``, if present. + + Available overrides: + * ``script_project``: inserts commands before ``prj_project save`` in Tcl script. + * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script. + * ``add_preferences``: inserts commands in LPF file. + * ``add_constraints``: inserts commands in XDC file. + + Build products: + * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log. + * ``{{name}}.bit``: binary bitstream. + * ``{{name}}.svf``: JTAG programming vector. """ - toolchain = "Trellis" + toolchain = None # selected when creating platform device = abstractproperty() package = abstractproperty() speed = abstractproperty() + grade = "C" # [C]ommercial, [I]ndustrial + + # Trellis templates _nextpnr_device_options = { "LFE5U-12F": "--25k", @@ -64,7 +91,7 @@ class LatticeECP5Platform(TemplatedPlatform): "BG756": "caBGA756", } - file_templates = { + _trellis_file_templates = { **TemplatedPlatform.build_script_templates, "{{name}}.il": r""" # {{autogenerated}} @@ -98,7 +125,7 @@ class LatticeECP5Platform(TemplatedPlatform): {% endfor %} """ } - command_templates = [ + _trellis_command_templates = [ r""" {{get_tool("yosys")}} {{quiet("-q")}} @@ -127,6 +154,107 @@ class LatticeECP5Platform(TemplatedPlatform): """ ] + # Diamond templates + + _diamond_file_templates = { + **TemplatedPlatform.build_script_templates, + "build_{{name}}.sh": r""" + # {{autogenerated}} + set -e{{verbose("x")}} + if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi + if [ -n "$NMIGEN_{{platform.toolchain}}_env" ]; then + bindir=$(dirname "$NMIGEN_{{platform.toolchain}}_env") + . "$NMIGEN_{{platform.toolchain}}_env" + fi + {{emit_commands("sh")}} + """, + "{{name}}.v": r""" + /* {{autogenerated}} */ + {{emit_design("verilog")}} + """, + "{{name}}.tcl": r""" + prj_project new -name "{{name}}" -impl "impl" -impl_dir "top_impl" \ + -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \ + -lpf "{{name}}.lpf" \ + -synthesis synplify + {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} + prj_src add "{{file}}" + {% endfor %} + prj_src add "{{name}}.v" + prj_impl option top "{{name}}" + prj_src add "{{name}}.sdc" + {{get_override("script_project")|default("# (script_project placeholder)")}} + prj_project save + prj_run Synthesis -impl "impl" -forceAll + prj_run Translate -impl "impl" -forceAll + prj_run Map -impl "impl" -forceAll + prj_run PAR -impl "impl" -forceAll + prj_run Export -impl "impl" -forceAll -task Bitgen + {{get_override("script_after_export")|default("# (script_after_export placeholder)")}} + """, + "{{name}}.lpf": r""" + # {{autogenerated}} + BLOCK ASYNCPATHS; + BLOCK RESETPATHS; + {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%} + LOCATE COMP "{{port_name}}" SITE "{{pin_name}}"; + IOBUF PORT "{{port_name}}" + {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %}; + {% endfor %} + {% for signal, frequency in platform.iter_clock_constraints() -%} + FREQUENCY PORT "{{signal.name}}" {{frequency/1000000}} MHZ; + {% endfor %} + {{get_override("add_preferences")|default("# (add_preferences placeholder)")}} + """, + "{{name}}.sdc": r""" + {% for signal, frequency in platform.iter_clock_constraints() -%} + create_clock -period {{1000000000/frequency}} [get_ports {{signal.name}}] + {% endfor %} + {{get_override("add_constraints")|default("# (add_constraints placeholder)")}} + """, + } + _diamond_command_templates = [ + # These don't have any usable command-line option overrides. + r""" + {{get_tool("pnmainc")}} + {{name}}.tcl + """, + r""" + {{get_tool("ddtcmd")}} + -oft -bit + -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit + """, + r""" + {{get_tool("ddtcmd")}} + -oft -svfsingle -revd -op "Fast Program" + -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf + """, + ] + + # Common logic + + def __init__(self, *, toolchain="Diamond"): + super().__init__() + + assert toolchain in ("Trellis", "Diamond") + self.toolchain = toolchain + + @property + def file_templates(self): + if self.toolchain == "Trellis": + return self._trellis_file_templates + if self.toolchain == "Diamond": + return self._diamond_file_templates + assert False + + @property + def command_templates(self): + if self.toolchain == "Trellis": + return self._trellis_command_templates + if self.toolchain == "Diamond": + return self._diamond_command_templates + assert False + def create_missing_domain(self, name): # No additional reset logic needed. return super().create_missing_domain(name) @@ -187,19 +315,19 @@ class LatticeECP5Platform(TemplatedPlatform): o_Q=q[bit] ) - def get_ineg(y, invert): + def get_ineg(z, invert): if invert: - a = Signal.like(y, name_suffix="_n") - m.d.comb += y.eq(~a) + a = Signal.like(z, name_suffix="_n") + m.d.comb += z.eq(~a) return a else: - return y + return z def get_oneg(a, invert): if invert: - y = Signal.like(a, name_suffix="_n") - m.d.comb += y.eq(~a) - return y + z = Signal.like(a, name_suffix="_n") + m.d.comb += z.eq(~a) + return z else: return a -- 2.30.2