From 3d6f1c59e70df22b604249e91cb5ea78f2c067db Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 17:34:32 +0000 Subject: [PATCH] whoops, fake pll/mem need vss/vdd --- experiments10_verilog/pll.py | 4 ++++ experiments9/LibreSOCMem.py | 6 ++++-- experiments9/pll.py | 4 ++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py index 56163ae..03a6ccc 100644 --- a/experiments10_verilog/pll.py +++ b/experiments10_verilog/pll.py @@ -224,7 +224,11 @@ def _load(): 'a1': Net.create(cell, 'a1'), 'vco_test_ana': Net.create(cell, 'vco_test_ana'), 'out_v': Net.create(cell, 'out_v'), + 'vdd': Net.create(cell, 'vdd'), + 'vss': Net.create(cell, 'vss'), } + nets['vdd'].setGlobal(True) + nets['vss'].setGlobal(True) # set net directions nets['ref_v'].setDirection( Net.Direction.IN ) diff --git a/experiments9/LibreSOCMem.py b/experiments9/LibreSOCMem.py index 8489df4..4c4753d 100644 --- a/experiments9/LibreSOCMem.py +++ b/experiments9/LibreSOCMem.py @@ -219,9 +219,11 @@ def _load(): nets = { '*': Net.create(cell, '*'), 'clk': Net.create(cell, 'clk'), - #'vdd': Net.create(cell, 'vdd'), - #'vss': Net.create(cell, 'vss'), + 'vdd': Net.create(cell, 'vdd'), + 'vss': Net.create(cell, 'vss'), } + nets['vss'].setGlobal(True) + nets['vdd'].setGlobal(True) for name, qty in (('a', 9), ('d', 64), ('q', 64), diff --git a/experiments9/pll.py b/experiments9/pll.py index 56163ae..03a6ccc 100644 --- a/experiments9/pll.py +++ b/experiments9/pll.py @@ -224,7 +224,11 @@ def _load(): 'a1': Net.create(cell, 'a1'), 'vco_test_ana': Net.create(cell, 'vco_test_ana'), 'out_v': Net.create(cell, 'out_v'), + 'vdd': Net.create(cell, 'vdd'), + 'vss': Net.create(cell, 'vss'), } + nets['vdd'].setGlobal(True) + nets['vss'].setGlobal(True) # set net directions nets['ref_v'].setDirection( Net.Direction.IN ) -- 2.30.2