From 3d7a397e9348cdfe064eaf4ba448806eadeca1d1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 19 Jun 2019 20:16:21 +0100 Subject: [PATCH] --- simple_v_extension/specification.mdwn | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 6e4e06331..3a705a90f 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2245,16 +2245,16 @@ of the RISC-V ISA, is as follows: VL/MAXVL/SubVL Block: -| 15 | 14:12 | 11:6 | 5:0 | -| - | ----- | ------ | ------- | -| rsvd | SubVL | MAXVL | VLEN | +| 31-30 | 29:28 | 27:22 | 21:16 | +| - | ----- | ------ | ------- | +| rsvd | SubVL | MAXVL | VLEN | Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: -| base+4 .. base+2 | base | number of bits | -| ------------------------- | ---------------- | -------------------------- | -| ..xxxx xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -| {ops}{Pred}{Reg}{VL} | SV Prefix | | +| base+4 | base+2 | base | number of bits | +| ------ | ------------------- | ---------------- | -------------------------- | +| ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | +| {ops}{Pred}{Reg} | VL Block | SV Prefix | | Notes: -- 2.30.2