From 3d9758479d99c0d88d13bcbb04bc0af6670051ba Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 23 May 2020 14:22:54 -0300 Subject: [PATCH] Choose between RA (src1) and zero immediate, conditioned on zero_a --- src/soc/experiment/compalu_multi.py | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 78407045..a4d87692 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Record +from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Record, Const from nmigen.hdl.rec import (DIR_FANIN, DIR_FANOUT) from nmutil.latch import SRLatch, latchregister @@ -247,7 +247,6 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # create list of src/alu-src/src-latch. override 1st and 2nd one below. # in the case, for ALU and Logical pipelines, we assume RB is the 2nd operand # in the input "regspec". see for example soc.fu.alu.pipe_data.ALUInputData - # TODO: assume RA is the 1st operand, zero_a detection is needed. sl = [] for i in range(self.n_src): sl.append([self.src_i[i], self.get_in(i), src_l.q[i]]) @@ -255,11 +254,19 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # if the operand subset has "zero_a" we implicitly assume that means # src_i[0] is an INT register type where zero can be multiplexed in, instead. # see https://bugs.libre-soc.org/show_bug.cgi?id=336 - #if hasattr(oper_r, "zero_a"): + if hasattr(oper_r, "zero_a"): # select zero immediate if opcode says so. however also change the latch # to trigger *from* the opcode latch instead. - # ... - # ... + op_is_imm = oper_r.zero_a + src1_or_imm = Signal(self.cu._get_srcwid(0), reset_less=True) + src1_zero_imm = Const(0, src1_or_imm.shape()) # zero immediate + src_sel = Signal(reset_less=True) + m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q[0])) + m.d.comb += src1_or_imm.eq(Mux(op_is_imm, src1_zero_imm, + self.src1_i)) + # overwrite 1st src-latch with immediate-muxed stuff + sl[0][0] = src1_or_imm + sl[0][2] = src_sel # if the operand subset has "imm_data" we implicitly assume that means # "this is an INT ALU/Logical FU jobbie, RB is multiplexed with the immediate" -- 2.30.2