From 3d9eafcfd6c839c13facb8300a62cea294553c89 Mon Sep 17 00:00:00 2001
From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0" <colepoirier@web>
Date: Tue, 23 Jun 2020 22:41:26 +0100
Subject: [PATCH]

---
 cole.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cole.mdwn b/cole.mdwn
index e0deb1f42..daf4019bb 100644
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -8,7 +8,7 @@ List of things that need more fleshed out bug reports:
 
 * Convert hand-drawn 180nm Test ASIC's Memory Layout diagram into editable SVG
 * Bperm tutorial
-* Bugseverywhere
+* Bugseverywhere (or also https://github.com/MichaelMure/git-bug/blob/master/bug/bug.go)
 * Competition to LS: Skywater 130nm production-ready PDK gets opensourced (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008254.html)
 * Memory bus/L1/L2 Cache documentation  (bug #397)
 * Scoreboard documentation (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html)
-- 
2.30.2